TC1167 Datasheet, PDF (112/127 Pages) Infineon Technologies AG – 32-Bit Single-Chip Microcontroller

TC1167
Electrical Parameters
With rising number m of clock cycles the maximum jitter increases linearly up to a value
of m that is defined by the K2-factor of the PLL. Beyond this value of m the maximum
accumulated jitter remains at a constant value. Further, a lower LMB-Bus clock
frequency f_LMB results in a higher absolute maximum jitter value.
Figure 26 gives the jitter curves for several K2 / f_LMB combinations.
±10.0
Dm
ns
±8.0
±7.0
±6.0
fLMB = 40 M H z (K 2 = 10 )
fLMB = 40 M H z (K2 = 20)
±4.0
fLMB = 80 M H z (K2 = 6)
±2.0
fLMB = 80 M H z (K2 = 10 )
±1.0
±0.0
0
fLMB = 133 M H z (K2 = 6 )
20
40
60
80
D m = M ax. jitter
m = N um ber of c ons ec utiv e f_LMB periods
K2 = K2- divider of PLL
100
120
oo
m
T C 1167 _PLL _J IT T_C
Figure 26
Approximated Maximum Accumulated PLL Jitter for Typical LMB-
Bus Clock Frequencies f_LMB
Note: The specified PLL jitter values are valid if the capacitive load per output pin does
not exceed C_L = 20 pF with the maximum driver and sharp edge. In case of
applications with many pins with high loads, driver strengths and toggle rates the
specified jitter values could be exceeded.
Note: The maximum peak-to-peak noise on the pad supply voltage, measured between
V_DDOSC3 at pin 106 and V_SSOSC at pin 104, is limited to a peak-to-peak voltage of
V_PP = 100 mV for noise frequencies below 300 KHz and V_PP = 40 mV for noise
frequencies above 300 KHz.
The maximum peak-to peak noise on the pad supply votage, measured between
V_DDOSC at pin 105 and V_SSOSC at pin 104, is limited to a peak-to-peak voltage of
V_PP = 100 mV for noise frequencies below 300 KHz and V_PP = 40 mV for noise
frequencies above 300 KHz.
Data Sheet
107
V1.3, 2009-10