TC1167 Datasheet, PDF (119/127 Pages) Infineon Technologies AG – 32-Bit Single-Chip Microcontroller

TC1167
Electrical Parameters
Table 22
Parameter
MLI Transmitter/Receiver Timing
(Operating Conditions apply), C_L = 50 pF
Symbol
Values
Min.
Typ. Max.
Unit Note /
Test Co
ndition
MLI Transmitter Timing
TCLK clock period
TCLK high time
TCLK low time
TCLK rise time
TCLK fall time
TDATA/TVALID output
delay time
t₁₀ CC 2 × T_MLI –
–
ns ¹⁾
t_{11 CC} 0.45 × t₁₀ 0.5 × t₁₀ 0.55 × t₁₀ ns ²⁾³⁾
t₁₂ CC 0.45 × t₁₀ 0.5 × t₁₀ 0.55 × t₁₀ ns ²⁾³⁾
t₁₃ CC –
–
4)
ns –
t₁₄ CC –
–
4)
ns –
t₁₅ CC -3
–
4.4
ns –
TREADY setup time to
t₁₆ SR 18
–
–
TCLK rising edge
ns –
TREADY hold time from t₁₇ SR 0
TCLK rising edge
–
–
ns –
MLI Receiver Timing
RCLK clock period
t₂₀
RCLK high time
t₂₁
RCLK low time
t₂₂
RCLK rise time
t₂₃
RCLK fall time
t₂₄
RDATA/RVALID setup
t₂₅
time to RCLK falling edge
SR 1 × T_MLI
SR –
SR –
SR –
SR –
SR 4.2
–
–
0.5 × t₂₀ –
0.5 × t₂₀ –
–
4
–
4
–
–
ns ¹⁾
ns ⁵⁾⁶⁾
ns ⁵⁾⁶⁾
ns ⁷⁾
ns ⁷⁾
ns –
RDATA/RVALID hold time t₂₆ SR 2.2
–
–
from RCLK rising edge
ns –
RREADY output delay time t₂₇ CC 0
–
16
ns –
1) T_MLImin. = T_SYS = 1/f_SYS. When f_SYS = 80 MHz, t₁₀ = 25 ns and t₂₀ = 12.5 ns.
2) The following formula is valid: t₁₁ + t₁₂ = t₁₀
3) The min./max. TCLK low/high times t₁₁/t₁₂ include the PLL jitter of f_SYS. Fractional divider settings must be
regarded additionally to t₁₁/t₁₂.
4) For high-speed MLI interface, strong driver sharp edge selection (class A2 pad) is recommended for TCLK.
5) The following formula is valid: t₂₁ + t₂₂ = t₂₀
6) The min. and max. value of is parameter can be adjusted by considering the other receiver timing parameters.
Data Sheet
114
V1.3, 2009-10