TLE7263E Datasheet, PDF (41/63 Pages) Infineon Technologies AG – Integrated HS-CAN, LIN, LDO and HS Switch System Basis Chip

TLE 7263E
Electrical Characteristics
Table 13 Electrical Characteristics (cont’d)
V_S = 13.5 V; I_CC1 = 1 mA; 4.9 V < V_CC1/2 < 5.1 V; SBC Active Mode; all outputs open;
-40 °C < T_j < 150 °C (max. 125 °C for CAN circuit characteristics); all voltages with
respect to ground; positive current defined flowing into pin; unless otherwise specified.
Parameter
Symbol Limit Values Unit Test Condition
Min. Typ. Max.
LIN Transceiver Characteristics
Receive Output RxD
HIGH level output
voltage
V_RxD,H
LOW level output
voltage
V_RxD,L
Transmission Input TxD
0.8 × –
V_CC1
–
–
–
V
0.2 × V
V_CC1
I_RxD(LIN) = -1.6 mA;
V_bus = V_S
I_RxD(LIN) = 1.6 mA;
V_bus = 0 V
HIGH level input voltage V_TxD,H
threshold
TxD input hysteresis V_TxD,hys
LOW level input voltage V_TxD,L
threshold
TxD pull-up Resistor R_TxD
Bus Receiver
–
–
0.8
0.3 × –
V_CC1
20 40
0.7 × V
V_CC1
1.5 V
–
V
recessive state
–
dominant state
80 kΩ V_TxD = 0 V
Receiver threshold
voltage, recessive to
dominant edge
V_bus,rd
0.42 0.48 × –
× V_S V_S
V–
Receiver dominant
state
Receiver threshold
voltage, dominant to
recessive edge
V_busdom –
V_bus,dr
–
–
0.40 V
× V_S
0.52 × 0.58 V
V_S
× V_S
(LIN Spec 1.3 (2.0);
Line 10.1.9 (3.1.9))
V_bus,rec < V_bus < 27 V
Receiver recessive
state
V_busrec
Receiver center voltage V_buscent
Receiver hysteresis
V_bus,hys
0.6 × –
–
–
V_S
0.475 0.5 × 0.525 V
× V_S V_S
× V_S
0.02 0.04 × 0.1 × V
× V_S V_S
V_S
(LIN Spec 1.3 (2.0);
Line 10.1.10 (3.1.10))
(LIN Spec 1.3 (2.0);
Line 10.1.11 (3.1.11))
V_bus,hys =
V_bus,rec - V_bus,dom
(LIN Spec 1.3 (2.0);
Line 10.1.12 (3.1.12))
Data Sheet
41
Rev. 1.51, 2007-06-22