TLE7263E Datasheet, PDF (26/63 Pages) Infineon Technologies AG – Integrated HS-CAN, LIN, LDO and HS Switch System Basis Chip

TLE 7263E
Features
4.12
Window Watchdog, Reset
When the output voltage V_cc1 exceeds the reset threshold voltage the reset output RO is
switched HIGH after a delay time of typ. 5 ms. This is necessary for a defined start of the
microcontroller when the application is switched on. As soon as an undervoltage
condition of the output voltage (V_CC1 < V_RT) appears, the reset output RO is switched
LOW again. The LOW signal is guaranteed down to an output voltage V_CC1 ≥ 1 V. Please
refer to Figure 19, Reset Timing Diagram.
After the above described delayed reset (LOW to HIGH transition of RO) the window
watchdog circuit is started by opening a long open window of typ. 64 ms. The long open
window allows the microcontroller to run its initialization sequences and then to trigger
the watchdog via the SPI. A watchdog trigger is detected as a write access to the
“window watchdog period bit field” within the SPI control word. In order to distinguish the
watchdog from the cyclic sense/wake timing register the “Configuration Select Bits”
needs to be set accordingly (see “SPI (Serial Peripheral Interface)” on Page 21). The
trigger is accepted when the CSN input becomes HIGH after the transmission of the SPI
word.
A correct watchdog trigger results in starting the window watchdog by opening a closed
window with a width of 50% of the selected window watchdog reset period. This period,
selected via the window watchdog timing bit field, is in the range between 16 ms and
1008 ms. This closed window is followed by a open window, with a width of 50% of the
selected period. From now on the microcontroller has to service the watchdog by
periodically writing to the window watchdog timing bit field. This write access has to meet
the open window. A correct watchdog service immediately results in starting the next
closed window (see Figure 17 "Watchdog Time-Out Definitions" on Page 54, safe
trigger area).
Should the trigger signal not meet the open window a watchdog reset is created by
setting the reset output RO low (see Reset delay time t_RD). Then the watchdog again
starts by opening a long open window. In addition, a “window watchdog reset flag” is set
within the SPI until the next successful watchdog trigger to monitor a watchdog reset. For
fail safe reasons the TLE 7263E is automatically switched in SBC Standby mode if a
watchdog trigger failure occurs. This minimizes the power consumption in case of a
permanent faulty microcontroller.
In case of a watchdog reset the watchdog immediately starts with a long open window
in SBC Standby Mode.
When entering a low power mode the watchdog can be requested to be disabled via an
SPI bit (see “SPI (Serial Peripheral Interface)” on Page 21). Upon this request the
watchdog is only turned off once the current consumption at V_CC1 falls below the
“watchdog current threshold”.
Data Sheet
26
Rev. 1.51, 2007-06-22