ICS9LPRS511EGLF Datasheet, PDF (9/19 Pages) Integrated Device Technology – Low Power Programmable Timing Control Hub™ for P4™ processor

Integrated
Circuit
Systems, Inc.
ICS9LPRS511
Advance Information
I2C Table: Output Control Register
Byte 5
Name
Control Function
Bit 7
24_48Mhz
Output Control
RW
Bit 6
Diff AMP
Differential output
RW
Bit 5
Diff AMP
Amplitude Control
RW
Bit 4
Reserved
Reserved
RW
iAMT EN (only
applicable to revisions
Bit 3 _{H and J, otherwise}
iAMT Enable Control
RW
this is a reserved bit)
Bit 2
Reserved
Reserved
RW
Bit 1
Reserved
Reserved
RW
Bit 0
Load Control
IIC Load control
RW
0
Disable
00 = 600mV
10 = 800mV
-
Stoppable
-
-
Load
1
Enable
01 = 900mV
11 = 700mV
-
Free-running
-
-
Do not Load
PWD
A/B/C/D/E/H/J
1
1
0
0
0
0
0
0
I2C Table: Reserved Register
Byte 6
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Control Function
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Type
RW
RW
RW
RW
RW
RW
RW
RW
I2C Table: Revision and Vendor ID Register
Byte 7
Name
Control Function
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
RID3
RID2
RID1
RID0
VID3
VID2
VID1
VID0
Revision ID
VENDOR ID
Type
R
R
R
R
R
R
R
R
0
-
-
-
-
-
-
-
0
-
-
-
-
-
-
001 = ICS
-
1
-
-
-
-
-
-
-
-
1
-
-
-
-
-
-
-
-
PWD
A/B/C/D/E/H/J
0
0
0
0
0
0
0
0
PWD
A/B
0
0
0
0
0
0
0
1
PWD
C/D
0
0
1
0
0
0
0
1
PWD PWD PWD
EHJ
000
111
001
010
000
000
000
111
I2C Table: Byte Count Register
Byte 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Name
BC7
BC6
BC5
BC4
BC3
BC2
BC1
BC0
Control Function
Byte Count Programming
b(7:0)
Type
R
R
R
RW
RW
RW
RW
RW
0
1
Writing to this register will configure how many bytes will be
read back, default is 0F = 15 bytes.
PWD
A/B/C/D/E/H/J
0
0
0
0
1
1
1
1
I2C Table: Watch Dog Timer Control Register
Byte 9
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Name
HWD_EN
SWD_EN
WD Hard Status
WD Soft Status
WDTCtrl
Control Function
Watchdog Hard Alarm
Enable
Watchdog Soft Alarm
Enable
WD Hard Alarm Status
WD Soft Alarm Status
Watch Dog Alarm Time
base Control
Type
RW
RW
R
R
RW
0
Disable
Disable
Normal
Normal
290ms Base
1
Enable
Enable
Alarm
Alarm
1160ms Base
PWD
A/B/C/D/E/H/J
0
0
X
X
0
Bit 2
Bit 1
Bit 0
HWD2
HWD1
HWD0
WD Hard Alarm Timer Bit 2 RW
1
These bits represent X*290ms (or 1.16S) the watchdog timer
WD Hard Alarm Timer Bit 1 RW waits before it goes to alarm mode. Default is 7 X 290ms =
1
2s.
WD Hard Alarm Timer Bit 0 RW
1
1137—09/05/08
9