ICS9LPRS511EGLF Datasheet, PDF (2/19 Pages) Integrated Device Technology – Low Power Programmable Timing Control Hub™ for P4™ processor

Integrated
Circuit
Systems, Inc.
Pin Description
Pin# Pin Name
1 **RLATCH
2 GND
3 VDD
4 **GSEL/24.576Mhz
5 VDDPCI
6 GND
7 **DOC_1
8 PCICLK0
9 PCICLK1_3x
10 FSLB/PCICLK2_2x
11 SELRSET/RESET#/PCICLK3
12 PCICLK4
13 **DOC_0
14 VDD48
15 FSLA/USB_48MHz
16 *SEL24_48#/24_48Mhz
17 GND
18 Vtt_PwrGd/WOL_STOP#
19 DOT96T_LR/PCIeT_LR0
20 DOT96C_LR/PCIeC_LR0
21 GND
22 PCIeT_LR1
23 PCIeC_LR1
24 PCIeT_LR2
25 PCIeC_LR2
26 GND
27 PCIeT_LR3
28 PCIeC_LR3
29 PCIeT_LR4
30 PCIeC_LR4
31 GND
32 VDDPCIEX
1137—09/05/08
ICS9LPRS511
Advance Information
Type
IN
PWR
PWR
I/O
PWR
PWR
IN
OUT
OUT
Pin Description
Asynchronous input pin used in combination with VTTPWRGD signal to determine
whether to reset I2c.
Ground pin.
Power supply, nominal 3.3V
Latch input to select PCIEX0 and DOT96 output. GSEL = 1, selects DOT 96Mhz ;
GSEL = 0, selects PCIEX0. /
24.576Mhz clock output
Power supply for PCI clocks, nominal 3.3V
Ground pin.
Dynamic Over Clocking pin: real time frequency selection 0: Normal; 1: Frequency will
transition to a preprogrammed value in the I2c.
PCI clock output.
Programmable 3x strength PCICLK, default 2x
I/O
3.3V tolerant input for CPU frequency selection. Low voltage threshold inputs, see
input electrical characteristics for Vil_FS and Vih_FS values. / 3.3V PCI clock output.
I/O
OUT
IN
PWR
Latch select input pin. SELRSET = 0, selects PCICLK, SELRSET = 1 selects
RESET#
PCI clock output.
Dynamic Over Clocking pin: real time frequency selection 0: Normal; 1: Frequency will
transition to a preprogrammed value in the I2c.
Power pin for the 48MHz output.3.3V
I/O
3.3V tolerant input for CPU frequency selection. Refer to input electrical
characteristics for Vil_FS and Vih_FS values. / Fixed 48MHz USB clock output. 3.3V.
I/O
PWR
IN
OUT
OUT
PWR
OUT
OUT
OUT
OUT
PWR
OUT
OUT
OUT
OUT
PWR
PWR
Latched select input for 24/48MHz output / 24/48MHz clock output. 1=24MHz, 0 =
48MHz.
Ground pin.
This active high 3.3V LVTTL input is a level sensitive strobe used to determine when
latch inputs are valid and are ready to be sampled / Asynchronous active low input pin
that stops all outputs except free running 25Mhz
True clock of differential pair for 96.00MHz non-spreading DOT clock/ True clock of
PCIEX0 Clock pair - selectable by GSEL; both 0.75V differential pairs are 0.75V push-
pull outputs with integrated 33ohm series resistor.
Complementary clock of differential pair for 96.00MHz non-spreading DOT clock/
Complementary clock of PCIEX0 Clock pair - selectable by GSEL; both 0.75V
differential pairs are 0.75V push-pull outputs with integrated 33ohm series resistor.
Ground pin.
True clock of 0.75V differential push-pull PCI_Express pair with integrated 33ohm
series resistor
Complement clock of 0.75V differential push-pull PCI_Express pair with integrated
33ohm series resistor
True clock of 0.75V differential push-pull PCI_Express pair with integrated 33ohm
series resistor
Complement clock of 0.75V differential push-pull PCI_Express pair with integrated
33ohm series resistor
Ground pin.
True clock of 0.75V differential push-pull PCI_Express pair with integrated 33ohm
series resistor
Complement clock of 0.75V differential push-pull PCI_Express pair with integrated
33ohm series resistor
True clock of 0.75V differential push-pull PCI_Express pair with integrated 33ohm
series resistor
Complement clock of 0.75V differential push-pull PCI_Express pair with integrated
33ohm series resistor
Ground pin.
Power supply for PCI Express clocks, nominal 3.3V
2