ICS9LPRS511EGLF Datasheet, PDF (12/19 Pages) Integrated Device Technology – Low Power Programmable Timing Control Hub™ for P4™ processor

Integrated
Circuit
Systems, Inc.
ICS9LPRS511
Advance Information
I2C Table: Output Control Register
Byte 20
Name
Control Function
Type
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reserved
Reserved
Reserved
Reserved
PCIEX PLL TBEN
CPU PLL TBEN
Reserved
RESET Sync
Reserved
RW
Reserved
RW
Reserved
RW
Reserved
RW
PCIEX PLL Turbo Enable RW
CPU PLL Turbo Enable RW
Reserved
RW
Reset Synchronization
upon Reset (Byte 21)
RW
0
-
-
-
-
Disable
Disable
-
Disable
I2C Table: Synchronization Control Register
Byte 21
Name
Control Function
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PCIEX Source
SATA Source
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
PCIEX Source
SATA Source
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Type
RW
RW
RW
RW
RW
RW
RW
RW
0
PCIEX PLL
PCIEX PLL
-
-
-
-
-
-
1
-
-
-
-
Enable
Enable
-
Enable
PWD
A/B/C/D/E/H/J
0
0
0
0
0
0
0
0
1
CPU PLL
Fixed PLL
-
-
-
-
-
-
PWD
A/B
0
1
1
1
1
1
1
1
PWD
C/D/E/H
1
1
1
1
1
1
1
1
PWD
J
0
1
1
1
1
1
1
1
I2C Table: DOC pin control register
Byte 22
Name
Control Function
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PCIEX
CPU
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
PCIEX PLL DOC0 pin
control
CPU PLL DOC0 pin
control
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Type
RW
RW
RW
RW
RW
RW
RW
RW
0
Enabled
Enabled
-
-
-
-
-
-
1
Disabled
Disabled
-
-
-
-
-
-
PWD
A/B/C/D/E/H/J
1
0
0
0
0
0
1
1
I2C Table: CPU PLL DOC 1 N programming Register (DOC0 = 1)
Byte 23
Name
Control Function
Type
0
1
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
N Div10
N Div9
N Div8
N Div7
N Div6
N Div5
N Div4
N Div3
RW
RW
RW
N Divider Programming
Byte23 bit(7:0) and Byte11
RW
bit(7:6)
RW
RW
RW
RW
The decimal representation of M and N Divider in Byte 11
and 23 will configure the CPU PLL VCO frequency. VCO
Frequency = 14.318 x Ndiv(10:0)/Mdiv(5:0)
PWD
A/B/C/D/E/H/J
X
X
X
X
X
X
X
X
Bytes 24 and 25 are reserved
I2C Table: PCIEX PLL DOC 1 N programming Register (DOC0 = 1)
Byte 26
Name
Control Function
Type
0
1
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
N Div10
N Div9
N Div8
N Div7
N Div6
N Div5
N Div4
N Div3
RW
RW
RW
N Divider Programming
Byte26 bit(7:0) and Byte15
RW
bit(7:6)
RW
RW
RW
RW
The decimal representation of M and N Divider in Byte 15
and 26 will configure the PCIEX PLL VCO frequency. VCO
Frequency = 14.318 x Ndiv(10:0)/Mdiv(5:0)
PWD
A/B/C/D/E/H/J
X
X
X
X
X
X
X
X
1137—09/05/08
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