ICS9LPRS511EGLF Datasheet, PDF (1/19 Pages) Integrated Device Technology – Low Power Programmable Timing Control Hub™ for P4™ processor

Integrated
Circuit
Systems, Inc.
ICS9LPRS511
Advance Information
Low Power Programmable Timing Control Hub™ for P4™ processor
Recommended Application:
Low Power CK505 Programmable clock
Output Features:
• 2 - 0.8V differential push-pull CPU pairs
• 1 - 25 MHz
• 5 - PCI (33MHz)
• 1 - USB, 48MHz
• 1 - 24/48MHz
• 1 - REF, 14.318MHz
• 8 - PCIEX 0.8V differential push-pull pairs
• 1 - PCIEX/DOT96MHz selectable pairs
• 1 - SATACLK differential pair
• 1 - 24.576MHz output
Features/Benefits:
• Programmable output frequencies
• Programmable output skew.
• Programmable spread percentage for EMI control.
• Programmable watch dog safe frequency.
• Supports tight ppm accuracy clocks for Serial-ATA
• Supports spread spectrum modulation, ±0.25% center
spread.
• Uses external 14.318MHz crystal, external crystal load
caps are required for frequency tuning
• Low Power differential outputs (50ohm resistor to GND
not needed)
• Integrated 33Ω series resistor on all differential
outputs
Key Specifications:
• CPU outputs cycle-cycle jitter < 85ps
• PCIEX outputs cycle-cycle jitter < 125ps
• PCI outputs cycle-cycle jitter < 250ps
• +/- 300ppm frequency accuracy on CPU & PCIEX clocks
Functionality Table
Bit4 Bit3 Bit2 Bit1
FSLC FSLB
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
1
0
0
1
0
0
0
1
0
0
0
1
1
0
0
1
1
0
1
0
0
0
1
0
0
0
1
0
1
0
1
0
1
0
1
1
0
0
1
1
0
0
1
1
1
0
1
1
1
1
0
0
0
1
0
0
0
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
1
1
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
1
1
0
1
1
1
1
0
1
1
1
0
1
1
1
1
1
1
1
1
Bit0
FSLA
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
CPU
MHz
266.66
133.33
200.00
166.66
333.33
100.00
400.00
200.00
266.66
133.33
200.00
166.66
333.33
100.00
400.00
200.00
269.33
134.66
202.00
168.33
274.66
137.33
206.00
N/A
279.99
140.00
210.00
N/A
285.33
142.66
214.00
N/A
PCIEX
MHz
100.00
100.00
100.00
100.00
100.00
100.00
100.00
100.00
100.00
100.00
100.00
100.00
100.00
100.00
100.00
100.00
101.00
101.00
101.00
101.00
103.00
103.00
103.00
N/A
105.00
105.00
105.00
N/A
107.00
107.00
107.00
N/A
PCI
MHz
33.33
33.33
33.33
33.33
33.33
33.33
33.33
33.33
33.33
33.33
33.33
33.33
33.33
33.33
33.33
33.33
33.66
33.66
33.66
33.66
34.33
34.33
34.33
34.33
35.00
35.00
35.00
35.00
35.66
35.66
35.66
35.66
SATA
MHz
100.00
100.00
100.00
100.00
100.00
100.00
100.00
100.00
100.00
100.00
100.00
100.00
100.00
100.00
100.00
100.00
100.00
100.00
100.00
100.00
100.00
100.00
100.00
100.00
100.00
100.00
100.00
100.00
100.00
100.00
100.00
100.00
Pin Configuration
**RLATCH 1
GND 2
VDD 3
**GSEL/24.576Mhz 4
VDDPCI 5
GND 6
**DOC_1 7
PCICLK0 8
PCICLK1_3x 9
FSLB/PCICLK2_2x 10
SELRSET/RESET#/PCICLK3 11
PCICLK4 12
**DOC_0 13
VDD48 14
FSLA/USB_48MHz 15
*SEL24_48#/24_48Mhz 16
GND 17
Vtt_PwrGd/WOL_STOP# 18
DOT96T_LR/PCIeT_LR0 19
DOT96C_LR/PCIeC_LR0 20
GND 21
PCIeT_LR1 22
PCIeC_LR1 23
PCIeT_LR2 24
PCIeC_LR2 25
GND 26
PCIeT_LR3 27
PCIeC_LR3 28
PCIeT_LR4 29
PCIeC_LR4 30
GND 31
64 25Mhz_0F_2x/Freerun*
63 GND
62 VDD25Mhz
61 VDDSATA
60 SATACLKT_LR
59 SATACLKC_LR
58 GND
57 REF0_2x/FSLC
56 GND
55 X1
54 X2
53 VDDREF
52 SDATA
51 SCLK
50 GND
49 CPUT_LR0
48 CPUC_LR0
47 VDDCPU
46 CPUT_LR1
45 CPUC_LR1
44 VDDI/O
43 GNDA
42 VDDA
41 PCIeT_LR8
40 PCIeC_LR8
39 PCIeT_LR7
38 PCIeC_LR7
37 GND
36 PCIeT_LR6
35 PCIeC_LR6
34 PCIeT_LR5
VDDPCIEX 32
33 PCIeC_LR5
64-Pin TSSOP
* Internal Pull-Up Resistor
** Internal Pull-Down Resistor
RESET pin is 3.3V tolerant
1137–09/05/08
ADVANCE INFORMATION documents contain information on products in the formative or design phase development. Characteristic data and other specifications are design goals.
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