ICS9LPRS511EGLF Datasheet, PDF (8/19 Pages) Integrated Device Technology – Low Power Programmable Timing Control Hub™ for P4™ processor

Integrated
Circuit
Systems, Inc.
ICS9LPRS511
Advance Information
I2C Table: Frequency Select Register
Byte 0
Name
Control Function
Type
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
ROD
PCIEX_SS
CPU_SS
FS4
FS3
FSLC
FSLB
FSLA
Reset on Demand
RW
PCIEX PLL Spread Enable RW
CPU PLL Spread Enable RW
Freq Select Bit 4
RW
Freq Select Bit 3
RW
Freq Select Bit 2
RW
Freq Select Bit 1
RW
Freq Select Bit 0
RW
I2C Table: Frequency Select Register
Byte 1
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Name
SEL24_48
I2c RB
SELRSET
PCIEX PLL MNEN
CPU PLL MNEN
25Mhz_0F
Reserved
GSEL
Control Function
Type
Select 24_48Mhz
RW
Select I2c readback from RW
Select RESET
RW
PCIEX PLL M/N Enable RW
CPU PLL M/N Enable RW
Free-running control
during WOL_STOP
RW
Reserved
RW
GSEL selection
RW
I2C Table: Output Control Register
Byte 2
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Name
USB_48Mhz
PCIEXT/C8
SATACLK
PCICLK5
PCICLK4
PCICLK3
PCICLK2
Reserved
Control Function
Output Control
Output Control
Output Control
Output Control
Output Control
Output Control
Output Control
Reserved
I2C Table: Output Control Register
Byte 3
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Name
PCICLK1
PCICLK0
PCIEXT/C7
PCIEXT/C6
PCIEXT/C5
PCIEXT/C4
PCIEXT/C3
PCIEXT/C2
Control Function
Output Control
Output Control
Output Control
Output Control
Output Control
Output Control
Output Control
Output Control
I2C Table: Output Control Register
Byte 4
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
PCIEXT/C1
REF0
CPUCLK1
CPUCLK0
24.576Mhz
Bit 2 Dot96Mhz/PCIEXT/C0
Bit 1
Bit 0
25Mhz_0F
Reserved
Control Function
Output Control
Output Control
Output Control
Output Control
Output Control
Output Control
Output Control
Reserved
Type
RW
RW
RW
RW
RW
RW
RW
RW
Type
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
1137—09/05/08
0
Disable
OFF
OFF
1
Enable
ON
ON
See Table 1: Frequency Selection Table
0
48
Shadow RAM
PCICLK4
Disable
Disable
Stoppable
-
PCIEX0
0
Disable
Disable
Disable
Disable
Disable
Disable
Disable
-
0
Disable
Disable
Disable
Disable
Disable
Disable
Disable
Disable
0
Disable
Disable
Disable
Disable
Disable
Disable
Disable
-
1
24
Active RAM
Reset#
Enable
Enable
Free-running
-
DOT96Mhz
1
Enable
Enable
Enable
Enable
Enable
Enable
Enable
-
1
Enable
Enable
Enable
Enable
Enable
Enable
Enable
Enable
1
Enable
Enable
Enable
Enable
Enable
Enable
Enable
-
PWD
A/B
0
1
1
0
0
Latch
Latch
Latch
PWD
C/D/E/H/J
0
0
1
0
0
Latch
Latch
Latch
PWD
A/B/C/D/E/H/J
latch
1
latch
0
0
latch
0
latch
PWD
A/B/C/D/E/H/J
1
1
1
1
1
1
1
1
PWD
A/B/C/D/E/H/J
1
1
1
1
1
1
1
1
PWD
A/B/C/D/E/H/J
1
1
1
1
1
1
1
1
8