ICS9LPRS511EGLF Datasheet, PDF (13/19 Pages) Integrated Device Technology – Low Power Programmable Timing Control Hub™ for P4™ processor

Integrated
Circuit
Systems, Inc.
ICS9LPRS511
Advance Information
Bytes 27 and 28 are reserved
I2C Table: Programmable output divider Register
Byte 29
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Name
CPUDiv3
CPUDiv2
CPUDiv1
CPUDiv0
PCIEXDiv3
PCIEXDiv2
PCIEXDiv1
PCIEXDiv0
Control Function
Type
RW
CPU Divider Ratio
RW
Programming Bits
RW
RW
RW
PCIEX Divider Ratio
Programming Bits for CPU
RW
PLL
RW
RW
0
0000:/2
0001:/3
0010:/5
0011:/7
0000:/2
0001:/3
0010:/5
0011:/7
0100:/4
0101:/6
0110:/10
0111:/14
0100:/4
0101:/6
0110:/10
0111:/14
1
1000:/8
1001:/12
1010:/20
1011:/28
1000:/8
1001:/12
1010:/20
1011:/28
1100:/16
1101:/24
1110:/20
1111:/56
1100:/10
1101:/24
1110:/20
1111:/56
PWD
A/B/C/D/E/H/J
X
X
X
X
X
X
X
X
I2C Table: Programmable output divider Register
Byte 30
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Name
PCIEXDiv3
PCIEXDiv2
PCIEXDiv1
PCIEXDiv0
PCIDiv3
PCIDiv2
PCIDiv1
PCIDiv0
Control Function
PCIEX Divider Ratio
Programming Bits for
PCIEX PLL
PCI Divider Ratio
Programming Bits
Type
RW
RW
RW
RW
RW
RW
RW
RW
0
0000:/5
0001:/3
0010:/N/A
0011:/N/A
0000:/N/A
0001:/3
0010:/9
0011:/N/A
0100:/10
0101:/6
0110:/N/A
0111:/N/A
0100:/N/A
0101:/6
0110:/18
0111:/N/A
I2C Table: Strength Control Register
Byte 31
Name
Control Function
Type
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
25Str_1
25Str_0
REFStr_1
REFStr_0
PCIStr_1
PCIStr_0
PCIStr_1
PCIStr_0
25Mhz_0 Strength Control ^RW
RW
REFCLK0 Strength Control ^RW
RW
PCICLK1 Strength Control ^RW
RW
PCICLK2 Strength Control ^RW
RW
0
00 = tristated
01 = 0.1x
00 = tristated
01 = 0.1x
00 = tristated
01 = 2.00x
00 = tristated
01 = 0.1x
1
1000:/20
1001:/12
1010:/N/A
1011:/N/A
1000:/N/A
1001:/12
1010:/36
1011:/N/A
1100:/40
1101:/24
1110:/N/A
1111:/N/A
1100:/N/A
1101:/24
1110:/72
1111:/N/A
PWD
A/B/C/D/E/H/J
X
X
X
X
X
X
X
X
1
10 = 1.00x
11 = 2.00x
10 = 1.00x
11 = 2.00x
10 = 1.00x
11 = 3.00x
10 = 1.00x
11 = 2.00x
PWD
A/B/C/D/E/H/J
1
1
1
1
0
1
1
1
I2C Table: Skew programming Register
Byte 32
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Name
CPUSkw3
CPUSkw2
CPUSkw1
CPUSkw0
CPUSkw3
CPUSkw2
CPUSkw1
CPUSkw0
Control Function
CPUCLK0 Skew Control
(ps)
CPUCLK1 Skew Control
(ps)
Type
RW
RW
RW
RW
RW
RW
RW
RW
0
0000:0
0001:100
0010:200
0011:300
0000:0
0001:100
0010:200
0011:300
0100:400
0101:500
0110:600
0111:700
0100:400
0101:500
0110:600
0111:700
1
1000:800
1001:900
1010:1000
1011:1100
1000:800
1001:900
1010:1000
1011:1100
1100:1200
1101:1300
1110:1400
1111:1500
1100:1200
1101:1300
1110:1400
1111:1500
PWD
A/B/C/D/E/H/J
0
0
0
0
0
0
0
0
1137—09/05/08
13