ICS9LPRS511EGLF Datasheet, PDF (11/19 Pages) Integrated Device Technology – Low Power Programmable Timing Control Hub™ for P4™ processor

Integrated
Circuit
Systems, Inc.
ICS9LPRS511
Advance Information
I2C Table: PCIEX PLL Frequency Control Register
Byte 15
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Name
N Div2
N Div1
M Div5
M Div4
M Div3
M Div2
M Div1
M Div0
Control Function
N Divider Prog bit 2
N Divider Prog bit 1
M Divider Programming
bit (5:0)
Type
RW
RW
RW
RW
RW
RW
RW
RW
0
1
PWD
A/B/C/D/E/H/J
X
X
The decimal representation of M and N Divider in Byte 15
X
and 16 will configure the PCIEX PLL VCO frequency. Default
X
at power up = latch-in or Byte 0 Rom table. VCO Frequency
X
= 14.318 x Ndiv(10:0)/Mdiv(5:0)
X
X
X
I2C Table: PCIEX PLL Frequency Control Register (DOC0 = 0)
Byte 16
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Name
N Div10
N Div9
N Div8
N Div7
N Div6
N Div5
N Div4
N Div3
Control Function
Type
RW
RW
RW
N Divider Programming
Byte16 bit(7:0) and Byte15
RW
bit(7:6)
RW
RW
RW
RW
0
1
PWD
A/B/C/D/E/H/J
X
X
The decimal representation of M and N Divider in Byte 15
X
and 16 will configure the PCIEX PLL VCO frequency. Default
X
at power up = latch-in or Byte 0 Rom table. VCO Frequency
X
= 14.318 x Ndiv(10:0)/Mdiv(5:0)
X
X
X
I2C Table: PCIEX PLL Spread Spectrum Control Register
Byte 17
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Name
SSP7
SSP6
SSP5
SSP4
SSP3
SSP2
SSP1
SSP0
Control Function
Spread Spectrum
Programming bit(7:0)
Type
RW
RW
RW
RW
RW
RW
RW
RW
0
1
These Spread Spectrum bits in Byte 17 and 18 will program
the spread percentage of PCIEX PLL
PWD
A/B/C/D/E/H/J
X
X
X
X
X
X
X
X
I2C Table: PCIEX PLL Spread Spectrum Control Register
Byte 18
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Name
SSP15
SSP14
SSP13
SSP12
SSP11
SSP10
SSP9
SSP8
Control Function
Spread Spectrum
Programming bit(14:8)
Type
RW
RW
RW
RW
RW
RW
RW
RW
0
1
These Spread Spectrum bits in Byte 17 and 18 will program
the spread percentage of PCIEX PLL
PWD
A/B/C/D/E/H/J
0
X
X
X
X
X
X
X
I2C Table: PCIEX PLL Frequency Select Register
Byte 19
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Name
Reserved
Reserved
Reserved
FS4
FS3
FSLC
FSLB
FSLA
Control Function
Reserved
Reserved
Reserved
Freq Select Bit 4
Freq Select Bit 3
Freq Select Bit 2
Freq Select Bit 1
Freq Select Bit 0
Type
RW
RW
RW
RW
RW
RW
RW
RW
0
1
-
-
-
-
-
-
See Table 2: PCIEX PLL Frequency Selection Table
PWD
A/B/C/D/E/H/J
1
0
0
0
0
Latch
Latch
Latch
1137—09/05/08
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