ICS9LPRS511EGLF Datasheet, PDF (10/19 Pages) Integrated Device Technology – Low Power Programmable Timing Control Hub™ for P4™ processor

Integrated
Circuit
Systems, Inc.
ICS9LPRS511
Advance Information
I2C Table: WD Safe Frequency Control Register
Byte 10
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Name
SWD2
SWD1
SWD0
WD SF4
WD SF3
WD SF2
WD SF1
WD SF0
Control Function
WD Soft Alarm Timer Bit 2
WD Soft Alarm Timer Bit 1
WD Soft Alarm Timer Bit 0
Watch Dog Safe Freq
Programming bits
Type
0
1
PWD
A/B/C/D/E/H/J
RW These bits represent X*290ms (or 1.16S) the watchdog timer
1
RW waits before it goes to alarm mode. Default is 7 X 290ms =
1
RW
2s.
1
RW
0
RW
0
RW
Writing to these bit will configure the safe frequency as
Byte10 bit (4:0).
0
RW
0
RW
0
I²C Table: CPU PLL Frequency Control Register
Byte 11
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Name
N Div2
N Div1
M Div5
M Div4
M Div3
M Div2
M Div1
M Div0
Control Function
N Divider Prog bit 2
N Divider Prog bit 1
M Divider Programming
bit (5:0)
Type
RW
RW
RW
RW
RW
RW
RW
RW
0
1
PWD
A/B/C/D/E/H/J
X
X
The decimal representation of M and N Divider in Byte 11
X
and 12 will configure the CPU PLL VCO frequency. Default
X
at power up = latch-in or Byte 0 Rom table. VCO Frequency
X
= 14.318 x Ndiv(10:0)/Mdiv(5:0)
X
X
X
I2C Table: CPU PLL Frequency Control Register (DOC0 = 0)
Byte 12
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Name
N Div10
N Div9
N Div8
N Div7
N Div6
N Div5
N Div4
N Div3
Control Function
Type
RW
RW
RW
N Divider Programming
Byte12 bit(7:0) and Byte11
RW
bit(7:6)
RW
RW
RW
RW
0
1
The decimal representation of M and N Divider in Byte 11
and 12 will configure the CPU PLL VCO frequency. Default
at power up = latch-in or Byte 0 Rom table. VCO Frequency
= 14.318 x Ndiv(10:0)/Mdiv(5:0)
PWD
A/B/C/D/E/H/J
X
X
X
X
X
X
X
X
I2C Table: CPU PLL Spread Spectrum Control Register
Byte 13
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Name
SSP7
SSP6
SSP5
SSP4
SSP3
SSP2
SSP1
SSP0
Control Function
Spread Spectrum
Programming bit(7:0)
Type
RW
RW
RW
RW
RW
RW
RW
RW
0
1
These Spread Spectrum bits in Byte 13 and 14 will program
the spread percentage of CPU PLL
PWD
A/B/C/D/E/H/J
X
X
X
X
X
X
X
X
I2C Table: CPU PLL Spread Spectrum Control Register
Byte 14
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Name
SSP15
SSP14
SSP13
SSP12
SSP11
SSP10
SSP9
SSP8
Control Function
Spread Spectrum
Programming bit(14:8)
Type
RW
RW
RW
RW
RW
RW
RW
RW
0
1
These Spread Spectrum bits in Byte 13 and 14 will program
the spread percentage of CPU PLL
PWD
A/B/C/D/E/H/J
0
X
X
X
X
X
X
X
1137—09/05/08
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