ICS9LPRS511EGLF Datasheet, PDF (4/19 Pages) Integrated Device Technology – Low Power Programmable Timing Control Hub™ for P4™ processor

Integrated
Circuit
Systems, Inc.
ICS9LPRS511
Advance Information
General Description
ICS9LPRS511 follows the Intel CK505-compliant clock specification. This clock synthesizer provides a single chip solution for
next generation P4 Intel processors and Intel chipsets. ICS9LPRS511 is driven with a 14.318MHz crystal.
Block Diagram
X1
XTAL
X2
SCLK
SDATA
FSLA
FSLB
FSLC
VttPwrgd/WOL_STOP#
DOC (1:0)
SEL24_48#
SELRSET
RLATCH
GSEL
Control
Logic
Fixed PLL
Frequency
Dividers
PLL
Array
Programmable
Frequency
Divider
Array
STOP
Logic
24.576MHz
25MHz
48MHz, USB
24_48MHz
DOTCLKT96/PCIEXT0
DOTCLKC96/PCIEXC0
REF0
PCICLK (4:0)
CPUCLKT (1:0)
CPUCLKC (1:0)
SATACLKT
SATACLKC
PCIEXT(8:1)
PCIEXC(8:1)
Reset#
1137—09/05/08
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