ICS9LPRS511EGLF Datasheet, PDF (19/19 Pages) Integrated Device Technology – Low Power Programmable Timing Control Hub™ for P4™ processor

Integrated
Circuit
Systems, Inc.
ICS9LPRS511
Advance Information
Revision History
Rev. Issue Date Description
Page #
0.1 8/3/2005 Initial Release
-
0.2 8/17/2005 Updated pinout and invert VTTPWRGD/WOL_STOP polarity 1-4
0.3 8/25/2005 Added I2c Tables
8-21
0.4 8/31/2005 Updated pinout (DOC1 removed, PCICLK1 added)
1-3, 19-21
1) Updated pinout, pin description (move freerun latch from
PCICLK to 25Mhz_0)
0.5 9/19/2005 2) Updated I2c Bytes 1, 5, 22, 31
1-3, 8-18
1) Changed pin 42, 53, 61 and 62 from Standby (Non
Collapsible) Power to Standard Power.
1,3,
0.6 10/6/2005 2) Removed Power Groups Table.
4
0.7 4/7/2006 Updated I2C.
8-18
1. Updated Pinout.
0.5 7/31/2006 2. Updated Pin Description.
1,2
0.6 9/26/2006 1. Updated I2C.
8-13
1. Updated Output Features to represent low power.
0.7 11/2/2006 2. Updated I2C.
Various
0.8 10/4/2007 Updated Functionality and CPU frequency table
1, 5
0.9 9/5/2008 Added Case Temperature @ 115C to Max Rating Table.
14
Silicon Revision History
Rev.
B0b6 = 1 in revisions [A:B]
0.1 B0b6 = 0 in revisions [C:J]
B7 = 01h in revisions [A:B]
B7 = 21h in revisions [C:D]
B7 = 41h in revision E
B7 = 51h in revision H
0.2 B7 = 61h in revision J
B21b7 = 0 in revisions [A:B]
B21b7 = 1 in revisions [C:H]
0.3 B21b7 = 0 in revision J
Description
1137—09/05/08
This product is protected by United States Patent NO. 7,342,420 and other patents.
19