ICS9LPRS511EGLF Datasheet, PDF (5/19 Pages) Integrated Device Technology – Low Power Programmable Timing Control Hub™ for P4™ processor

Integrated
Circuit
Systems, Inc.
Table1: CPU PLL Frequency Selection Table
B0b4 B0b3 B0b2 B0b1 B0b0
CPU
PCIEX
(B21b7 = 1)
Spread
FSLC FSLB FSLA MHz
MHz %
0
0
0
0
0
266.66
100.00 _{0-0.5% Down}
0
0
0
0
1
133.33
100.00 _{0-0.5% Down}
0
0
0
1
0
200.00
100.00 _{0-0.5% Down}
0
0
0
1
1
166.66
100.00 _{0-0.5% Down}
0
0
1
0
0
333.33
100.00 _{0-0.5% Down}
0
0
1
0
1
100.00
100.00 _{0-0.5% Down}
0
0
1
1
0
400.00
100.00 _{0-0.5% Down}
0
0
1
1
1
200.00
100.00 _{0-0.5% Down}
0
1
0
0
0
266.66
100.00 _{+/-0.25% Center}
0
1
0
0
1
133.33
100.00 _{+/-0.25% Center}
0
1
0
1
0
200.00
100.00 _{+/-0.25% Center}
0
1
0
1
1
166.66
100.00 _{+/-0.25% Center}
0
1
1
0
0
333.33
100.00 _{+/-0.25% Center}
0
1
1
0
1
100.00
100.00 _{+/-0.25% Center}
0
1
1
1
0
400.00
100.00 _{+/-0.25% Center}
0
1
1
1
1
200.00
100.00 _{+/-0.25% Center}
1
0
0
0
0
269.33
101.00 _{+/- 0.3% Center}
1
0
0
0
1
134.66
101.00 _{+/- 0.3% Center}
1
0
0
1
0
202.00
101.00 _{+/- 0.3% Center}
1
0
0
1
1
168.33
101.00 _{+/- 0.3% Center}
1
0
1
0
0
274.66
103.00 _{+/- 0.3% Center}
1
0
1
0
1
137.33
103.00 _{+/- 0.3% Center}
1
0
1
1
0
206.00
103.00 _{+/- 0.3% Center}
1
0
1
1
1
N/A
N/A _{+/- 0.3% Center}
1
1
0
0
0
279.99
105.00 _{+/- 0.3% Center}
1
1
0
0
1
140.00
105.00 _{+/- 0.3% Center}
1
1
0
1
0
210.00
105.00 _{+/- 0.3% Center}
1
1
0
1
1
N/A
N/A _{+/- 0.3% Center}
1
1
1
0
0
285.33
107.00 _{+/- 0.3% Center}
1
1
1
0
1
142.66
107.00 _{+/- 0.3% Center}
1
1
1
1
0
214.00
107.00 _{+/- 0.3% Center}
1
1
1
1
1
N/A
N/A _{+/- 0.3% Center}
ICS9LPRS511
Advance Information
1137—09/05/08
5