ICS1894-32_1 Datasheet, PDF (9/53 Pages) Integrated Device Technology – 10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE

ICS1894-32
10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE
PHY is capable of detecting, and that may otherwise be
undetectable by the MAC sub-layer) was detected
somewhere in the frame presently being transferred from
the PHY. RXER transitions synchronously with respect to
RXC. While RXDV is de-asserted, RXER has no effect on
the MAC.
Reduced MII (RMII) Data Interface
The Reduced Media Independent Interface (RMII) specifies
a low pin count Media Independent Interface (MII). It
provides a common interface between physical layer and
MAC layer devices, and has the following key
characteristics:
• Supports 10Mbps and 100Mbps data rates.
• Uses a single 50MHz reference clock provided by the
MAC or the system board.
• Provides independent 2-bit wide (di-bit) transmit and
receive data paths.
• Contains two distinct groups of signals: one for
transmission and the other for reception.
In RMII mode, a 50 MHz reference clock is connected to
REFIN(pin 30).
PHYCEIVER
IDT® 10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE
9
ICS1894-32 REV G 020509