ICS1894-32_1 Datasheet, PDF (2/53 Pages) Integrated Device Technology – 10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE

ICS1894-32
10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE
Block Diagram
PHYCEIVER
10/100 MII/RMII
MAC
Interface
Interface
MUX
MII
Management
Interface
MII
Extended
Register
Set
PCS
• Framer
• CRS/COL
Detection
• Parallel to Serial
• 4B/5B
Low-Jitter
Clock
Synthesizer
Clock
100Base-T
PMA
• Clock Recovery
• Link Monitor
• Signal Detection
• Error Detection
10Base-T
Smart Power
Control
Block
Power
TP_PMD
• MLT-3
• Stream Cipher
• Adaptive Equalizer
• Baseline Wander
Correction
Configuration
and Status
Integrated
Switch
Auto-
Negotiation
Twisted-
Pair
Interface to
Magnetics
Modules and
RJ45
Connector
LEDs and PHY
Address
Pin Assignment
TP_AP
TP_AN
VSS
VDD
TP_BN
TP_BP
VDD
TCSR
1
25
NLG32 With Ground
Connecting to Thermal Pad
9
17
TXD0
TXEN
SPEED/TXCLK
NOD/RXER
ANSEL/RXCLK
VDDIO
RMII/RXDV
FDPX/RXD0
32-pin 5mm x 5mm QFN
IDT® 10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE
2
ICS1894-32 REV G 020509