ICS1894-32_1 Datasheet, PDF (41/53 Pages) Integrated Device Technology – 10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE

ICS1894-32
10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE
PHYCEIVER
100M MII: Carrier Assertion/De-Assertion (Half-Duplex Transmission)
The table below lists the significant time periods for the 100M MII carrier assertion/de-assertion during half-duplex
transmission. The time periods consist of timings of signals on the following pins:
• TXEN
• TXCLK
• CRS
The 100M MII Carrier Assertion/De-Assertion Timing Diagram (Half-Duplex Transmission Only) shows the timing
diagram for the time periods.
Time
Period
t1
t2
Parameter
TXEN Sampled Asserted to CRS Assert
TXEN De-Asserted to CRS De-Asserted
Conditions Min. Typ. Max. Units
0
3
4 Bit times
0
3
4 Bit times
100M MII Carrier Assertion/De-Assertion Timing Diagram (Half-Duplex Transmission Only)
t2
TXEN
TXCLK
CRS
t1
IDT® 10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE
41
ICS1894-32 REV G 020509