ICS1894-32_1 Datasheet, PDF (5/53 Pages) Integrated Device Technology – 10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE

ICS1894-32
10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE
PHYCEIVER
Strapping Options
Pin
Number
Pin
Name
14
AMDIX/RXD3
15
P3/RXD2
11
P2/INT
31
P0/LED0
32
P1/LED1
16
RXTRI/RXD1
17
FDPX/RXD0
18
RMII/RXDV
20 ANSEL/RXCLK
21
NOD/RXER
22 SPEED/TXCLK
Pin
Type¹
Pin Function
IO/Ipu 1 = AMDIX enable
0 = AMDIX disable
IO/Ipd The PHY address is set by P[3:0] at power-on reset. P0 and P1 must have external
IO/Ipd ^{pull-up or pull-down to set address at start up.}
IO
IO
IO/Ipd 1 = Receiver Tristate Enable; 0 = Receiver Tristate Disable
IO/Ipu 1=Full duplex
0=Half duplex
Ignored if Auto negotiation is enabled
IO/Ipd 1 = RMII mode
0 = MII mode
IO/Ipu 1=Enable auto negotiation
0=Disable auto negotiation
IO/Ipd 0=Node mode
1=repeater mode
IO/Ipu 1=100M mode
0=10M mode
Ignored if Auto negotiation is enabled
1. IO/Ipu = Digital Input with internal 20k pull-up during power on reset/hardware reset; output pin otherwise.
2. IO/Ipd = Digital Input with internal 20k pull-down during power on reset/hardware reset; output pin otherwise.
Functional Description
The ICS1894-32 is an ethernet PHYceiver. During data
transmission, it accepts sequential nibbles/di-bits from the
MAC (Media Access Control), converts them into a serial bit
stream, encodes them, and transmits them over the medium
through an external isolation transformer. When receiving
data, the ICS1894-32 converts and decodes a serial bit
stream (acquired from an isolation transformer that
interfaces with the medium) into sequential nibbles/di-bits. It
subsequently presents these nibbles/di-bits to the MAC
Interface.
The ICS1894-32 implements the OSI model’s physical
layer, consisting of the following, as defined by the ISO/IEC
8802-3 standard:
• Physical Coding sublayer (PCS)
• Physical Medium Attachment sublayer (PMA)
• Physical Medium Dependent sublayer (PMD)
• Auto-Negotiation sublayer
The ICS1894-32 is transparent to the next layer of the OSI
model, the link layer. The link layer has two sublayers: the
Logical Link Control sublayer and the MAC sublayer. The
ICS1894-32 can interface directly with the MAC via MII/RMII
interface signals.
The ICS1894-32 transmits framed packets acquired from its
MAC Interface and receives encapsulated packets from
another PHY, which it translates and presents to its MAC
Interface.
Note:
As per the ISO/IEC standard, the
ICS1894-32 does not affect, nor is it
affected by, the underlying structure of the
MAC frame it is conveying.
IDT® 10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE
5
ICS1894-32 REV G 020509