ICS1894-32_1 Datasheet, PDF (44/53 Pages) Integrated Device Technology – 10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE

ICS1894-32
10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE
PHYCEIVER
100M Media Independent Interface: Input-to-Carrier Assertion/De-Assertion
The table below lists the significant time periods for the 100M MDI input-to-carrier assertion/de-assertion. The time
periods consist of timings of signals on the following pins:
• TP_RX (that is, TP_RXP and TP_RXN)
• CRS
• COL
The 100M MDI Input to Carrier Assertion/De-Assertion Timing Diagram shows the timing diagram for the time
periods.
Time
Period
Parameter
Conditions Min. Typ. Max. Units
t1 First Bit of /J/ into TP_RX to CRS Assert †
–
10 – 14 Bit times
t2 First Bit of /J/ into TP_RX while
Transmitting Data to COL Assert †
Half-Duplex Mode 9
– 13 Bit times
t3 First Bit of /T/ into TP_RX to CRS
De-Assert ‡
–
13 – 18 Bit times
t4 First Bit of /T/ Received into TP_RX to
COL De-Assert ‡
Half-Duplex Mode 13 – 18 Bit times
†The IEEE maximum is 20 bit times.
‡The IEEE minimum is 13 bit times, and the maximum is 24 bit times.
100M MDI Input to Carrier Assertion/De-Assertion Timing Diagram
First bit
First bit of /T/
TP_RX^†
t3
t1
CRS
COL
t2
t4
† _Shown
unscrambled.
IDT® 10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE
44
ICS1894-32 REV G 020509