ICS1894-32_1 Datasheet, PDF (43/53 Pages) Integrated Device Technology – 10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE

ICS1894-32
10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE
PHYCEIVER
100M MII Media Independent Interface: Receive Latency
The table below lists the significant time periods for the 100M MII/100M Stream Interface receive latency. The time
periods consist of timings of signals on the following pins:
• TP_RX (that is, TP_RXP and TP_RXN)
• RXCLK
• RXD (that is, RXD[3:0])
The 100M MII/100M Stream Interface: Receive Latency Timing Diagram shows the timing diagram for the time
periods.
Time
Period
Parameter
t1 First Bit of /J/ into TP_RX to /J/ on RXD
Conditions
100M MII
Min. Typ. Max. Units
– 16 17 Bit times
100M MII/100M Stream Interface: Receive Latency Timing Diagram
TP_RX^†
RXCLK
RXD
t1
† _Shown
unscrambled.
IDT® 10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE
43
ICS1894-32 REV G 020509