ICS1894-32_1 Datasheet, PDF (7/53 Pages) Integrated Device Technology – 10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE

ICS1894-32
10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE
PHYCEIVER
ICS1894-32 devices. Each ICS1894-32 device is
assigned a PHY address between 1 and 7 by the P[4:0]
strapping pins. P3 and P4 address bits are hardcoded to
‘0’ in design.
• An internal addressable set of thirty-one 8-bit MDIO
registers. Register [0:6] are required, and their functions
are defined by the IEEE 802.3u Specification. The
additional registers are provided for expanded
functionality.
The ICS1894-32 supports MIIM in both MII mode and RMII
mode.
The following table shows the MII Management frame
format for the ICS1894-32.
MII Management Frame Format
Preamble Start of Read/Write PHY Address REG Address TA
Frame OP Code Bits [4:0]
Bits [4:0]
Data Bits
Idle
[15:0]
Read 32 1’s
01
10
00AAA
RRRRR
Z0 DDDDDDDD_DDDDDDDD Z
Write 32 1’s
01
01
00AAA
RRRRR
10 DDDDDDDD_DDDDDDDD Z
Interrupt (INT)
P2/INT (pin 11) is an optional interrupt signal that is used to
inform the external controller that there has been a status
update in the ICS1894-32 PHY register. Register 23 shows
the status of the various interrupts while register 22 controls
the enabling/disabling of the interrupts.
MII Data Interface
The Media Independent Interface (MII) is specified in
Clause 22 of the IEEE 802.3u Specification. It provides a
common interface between physical layer and MAC layer
devices, and has the following key characteristics:
• Supports 10Mbps and 100Mbps data rates.
• Uses a 25MHz reference clock, sourced by the PHY.
• Provides independent 4-bit wide (nibble) transmit and
receive data paths.
• Contains two distinct groups of signals: one for
transmission and the other for reception.
The ICS1894-32 is configured for MII mode upon power-up
or hardware reset with the following:
• A 25MHz crystal connected to REFIN, REFOUT (pins 30,
29), or an external 25MHz clock source (oscillator)
connected to REFIN
IDT® 10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE
7
ICS1894-32 REV G 020509