ICS1894-32_1 Datasheet, PDF (34/53 Pages) Integrated Device Technology – 10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE

ICS1894-32
10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE
PHYCEIVER
Timing for Transmit Clock (TXCLK) Pin
The table below lists the significant time periods for signals on the Transmit Clock (TXCLK) pin. The Transmit Clock
Timing Diagram figure shows the timing diagram for the time periods.
Time
Period
Parameter
t1 TXCLK Duty Cycle
t2a TXCLK Period
t2b TXCLK Period
Conditions
–
100M MII (100Base-TX)
10M MII (10Base-T)
Min. Typ. Max. Units
35 50 65
%
– 40 –
ns
– 400 –
ns
Transmit Clock Timing Diagram
t1
TXCLK
t2x
Timing for Receive Clock (RXCLK) Pin
The table below lists the significant time periods for signals on the Receive Clock (RXCLK) pin. The Receive Clock
Timing Diagram figure shows the timing diagram for the time periods.
Time
Period
Parameter
t1 RXCLK Duty Cycle
t2a RXCLK Period
t2b RXCLK Period
Conditions
–
100M MII (100Base-TX)
10M MII (10Base-T)
Min. Typ. Max. Units
35 50 65 %
– 40 –
ns
– 400 –
ns
Receive Clock Timing Diagram
t1
RXCLK
t2
IDT® 10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE
34
ICS1894-32 REV G 020509