ICS1894-32_1 Datasheet, PDF (40/53 Pages) Integrated Device Technology – 10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE

ICS1894-32
10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE
PHYCEIVER
100M / MII Media Independent Interface: Transmit Latency
The table below lists the significant time periods for the MII/100 Stream Interface transmit latency. The time periods
consist of timings of signals on the following pins:
• TXEN
• TXCLK
• TXD (that is, TXD[3:0])
• TP_TX (that is, TP_TXP and TP_TXN)
The MII/100M Stream Interface Transmit Latency Timing Diagram shows the timing diagram for the time periods.
Time
Period
Parameter
t1 TXEN Sampled to MDI Output of First
Bit of /J/ †
Conditions
MII mode
Min. Typ. Max. Units
– 2.8 3 Bit times
†The IEEE maximum is 18 bit times.
MII/100M Stream Interface Transmit Latency Timing Diagram
TXEN
TXCLK
TXD
Preamble /J/ Preamble /K/
TP_TX^†
t1
† _Shown
unscrambled.
IDT® 10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE
40
ICS1894-32 REV G 020509