ICS1894-32_1 Datasheet, PDF (28/53 Pages) Integrated Device Technology – 10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE

ICS1894-32
10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE
PHYCEIVER
Bit
Definition
When Bit = 0
When Bit = 1
Access ² SF² Default³ Hex
Register 25h - Extended Control Register
25.15:12
Reserved
Reserved
RW
0
0
25.11
Reserved
Reserved
RW
0
6
25.10
Reserved
Reserved
RW
1
25.9
TX10BIAS_SET
The normal output current of the Bias block for
RW
25.8
10BaseT is 540uA. Changing the register can modify
the current with a step size of 5%
25.7
000: output 80% current
001: output 85% current
010: output 90% current
011: output 95% current
100: output 100% current
101: output 105% current
110: output 110% current
111: output 115% current
1
0
0
4
25.6
TX100BIAS_SET The normal output current of the Bias block for
RW
1
25.5
100BaseTX is 180uA. Changing the register can
modify the current with a step size of 5%
0
25.4
000: output 80% current
0
001: output 85% current
010: output 90% current
011: output 95% current
100: output 100% current
101: output 105% current
110: output 110% current
111: output 115% current
25.3
OUTDLY_CTL
This register controls the delay time of the digital
RW
25.2
control signal for xmit_dac.
00: Longest delay time (same as original design)
01: Long delay time
10: Short delay time
11: Shortest delay time
0
1
25.1
Reserved
Reserved
RW
0
25.0
1
Register 26 - 31h - Extended Control Register (Reserved)
Note 1: Ignored if Auto negotiation is enabled.
Note 2: CW = Command Override Write
LH = Latching High
LL = Latching Low
LMX = Latching Maximum
RO = Read Only
RW = Read/Write
RW/0 = Read/Write Zero
RW/1 = Read/Write One
SC = Self-clearing
SF = Special Functions
Note 3: L = Latched on power-up/hardware reset
† = the default state of the pin at reset
IDT® 10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE
28
ICS1894-32 REV G 020509