843N001I Datasheet, PDF (9/20 Pages) Integrated Device Technology – Low Voltage, LVCMOS/LVPECL-to-LVPECL/ECL Clock Generator

873991-147 DATA SHEET
2V
2V
V,
CC
V
CCO
V
CCA
PARAMETER MEASUREMENT INFORMATION
V
CC
nCLK
V
PP
CLK
Cross Points
V
CMR
-1.3V ± -0.165V
OUTPUT LOAD AC TEST CIRCUIT
OUTPUT SKEW
nQFB,
nQAx:nQDx
QFB,
QAx:QDx
hcyc n
hcyc n+1
| | ^{tjit(hcyc) = hcyc n – hcyc n+1}
1000 Cycles
HALF-CYCLE JITTER
nQxx
Qxx
nQyy
Qyy
tsk(ω)
MULTIPLE FREQUENCY SKEW
nQFB,
nQAx:nQDx
V
EE
DIFFERENTIAL INPUT LEVELS
nQFB,
nQAx:nQDx
QFB,
QAx:QDx
tcycle n
tcycle n+1
| | ^{tjit(cc) = tcycle n – tcycle n+1}
1000 Cycles
CYCLE-TO-CYCLE JITTER
OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
STATIC PHASE OFFSET
QFB,
QAx:QDx
OUTPUT RISE/FALL TIME
REVISION B 8/25/15
9
LOW VOLTAGE, LVCMOS/LVPECL-TO LVPECL/ECL
CLOCK GENERATOR