843N001I Datasheet, PDF (12/20 Pages) Integrated Device Technology – Low Voltage, LVCMOS/LVPECL-to-LVPECL/ECL Clock Generator

873991-147 DATA SHEET
RECOMMENDATIONS FOR UNUSED INPUT AND OUTPUT PINS
INPUTS:
OUTPUTS:
CLK/nCLK INPUTS
For applications not requiring the use of a differential input, both the
CLK and nCLK pins can be left floating.Though not required, but for
additional protection, a 1kΩ resistor can be tied from CLK to ground.
LVPECL OUTPUTS
All unused LVPECL outputs can be left floating. We recommend
that there is no trace attached. Both sides of the differential output
pair should either be left floating or terminated.
LVCMOS CONTROL PINS
All control pins have internal pullups or pulldowns; additional
resistance is not required but can be added for additional protection.
A 1kΩ resistor can be used.
TERMINATION FOR LVPECL OUTPUTS
The clock layout topology shown below is a typical termination for
LVPECL outputs. The two different layouts mentioned are recom-
mended only as guidelines.
FOUT and nFOUT are low impedance follower outputs that generate
ECL/LVPECL compatible outputs. Therefore, terminating resistors
(DC current path to ground) or current sources must be used for
functionality. These outputs are designed to drive 50Ω transmission
lines. Matched impedance techniques should be used to maximize
operating frequency and minimize signal distortion. Figures 5A
and 5B show two different layouts which are recommended only
as guidelines. Other suitable clock layouts may exist and it would
be recommended that the board designers simulate to guarantee
compatibility across all printed circuit and clock component process
variations.
FIGURE 5A. LVPECL OUTPUT TERMINATION
FIGURE 5B. LVPECL OUTPUT TERMINATION
REVISION B 8/25/15
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LOW VOLTAGE, LVCMOS/LVPECL-TO LVPECL/ECL
CLOCK GENERATOR