843N001I Datasheet, PDF (14/20 Pages) Integrated Device Technology – Low Voltage, LVCMOS/LVPECL-to-LVPECL/ECL Clock Generator

POWER CONSIDERATIONS
873991-147 DATA SHEET
This section provides information on power dissipation and junction temperature for the 873991-147.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the 873991-147 is the sum of the core power plus the analog power plus the power dissipated in the
load(s). The following is the power dissipation for V = 3.3V + 5% = 3.465V, which gives worst case results.
CC
NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
• Power (core) = V * (I + I
+ I ) = 3.465V * (150mA + 15mA + 95mA) = 900.9mW
MAX
CC_MAX
CC_MAX
CCA_MAX
CCO_MAX
• Power (outputs) = 30mW/Loaded Output pair
MAX
If all outputs are loaded, the total power is 14 * 30mW = 420mW
Total Power (3.465V, with all outputs switching) = 900.9mW + 420mW = 1.3209W
_MAX
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the
device. The maximum recommended junction temperature for HiPerClockS^TM devices is 125°C.
The equation for Tj is as follows: Tj = θJA * Pd_total + TA
Tj = Junction Temperature
θJA = Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
TA = Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming no air flow
and a multi-layer board, the appropriate value is 55.5°C/W per Table 7 below.
Therefore, Tj for an ambient temperature of 50°C with all outputs switching is:
50°C + 1.32W * 55.5°C/W = 123.3°C. This is at the limit of 125°C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow,
and the type of board (multi-layer).
TABLE 7. THERMAL RESISTANCE θJA FOR 52-PIN LQFP FORCED CONVECTION
θJA by Velocity (Meters per Second)
Multi-Layer PCB, JEDEC Standard Test Boards
0
55.5°C/W
1
50.1°C/W
2.5
47.0°C/W
REVISION B 8/25/15
14
LOW VOLTAGE, LVCMOS/LVPECL-TO LVPECL/ECL
CLOCK GENERATOR