843N001I Datasheet, PDF (3/20 Pages) Integrated Device Technology – Low Voltage, LVCMOS/LVPECL-to-LVPECL/ECL Clock Generator

873991-147 DATA SHEET
TABLE 1. PIN DESCRIPTIONS
Number
Name
Type
Description
1
V
Power
Negative supply pin.
EE
Active High Master Reset. When logic HIGH, the internal dividers are
2
MR
Input
Pulldown
reset causing the true outputs (Qx) to go low and the inverted outputs
(nQx) to go high. When logic LOW, the internal dividers and the outputs
are enabled. LVCMOS/LVTTL interface levels.
3
PLL_EN
Input
Pulldown
PLL enable pin. When logic LOW, PLL is enabled. When logic HIGH, PLL
is in bypass mode. LVCMOS/LVTTL interface levels.
Selects between the different reference inputs as the PLL reference
4
REF_SEL Input Pulldown source. When logic LOW, selects CLK/nCLK. When logic HIGH, selects
REF_CLK. LVCMOS/LVTTL interface levels.
5
FSEL_FB2
6
FSEL_FB1 Input Pulldown Feedback frequency select pins. LVCMOS/LVTTL interface levels.
7
FSEL_FB0
8
REF_CLK Input Pulldown Reference clock input. LVCMOS/LVTTL interface levels.
9
10
11
12
13
14
15
16
17, 22, 30, 42
18, 19
CLK
nCLK
V
CC
EXT_FB
nEXT_FB
V
CCA
nQFB
QFB
V
CCO
nQD0, QD0
Input
Input
Power
Input
Input
Power
Output
Power
Output
Pulldown Non-inverting differential clock input.
Pullup/
Pulldown
Inverting differential clock input. V /2 default when left floating.
CC
Core supply pin.
Pulldown Non-inverting external feedback input.
Pullup/
Pulldown
Inverting external feedback input. V /2 default when left floating.
CC
Analog supply pin.
Differential feedback output pair. LVPECL Interface levels.
Output supply pins.
Differential output pair. LVPECL interface levels.
20, 21
nQD1, QD1 Output
Differential output pair. LVPECL interface levels.
23, 24
nQC0, QC0 Output
Differential output pair. LVPECL interface levels.
25, 26
27
33
36
39
28, 29
nQC1, QC1
FSEL3
FSEL2
FSEL1
FSEL0
nQC2, QC2
Output
Input
Output
Differential output pair. LVPECL interface levels.
Pulldown Frequency select pins. LVCMOS/LVTTL interface levels.
Differential output pair. LVPECL interface levels.
31, 32
nQB0, QB0 Output
Differential output pair. LVPECL interface levels.
34, 35
nQB1, QB1 Output
Differential output pair. LVPECL interface levels.
37, 38
nQB2, QB2 Output
Differential output pair. LVPECL interface levels.
40, 41
nQB3, QB3 Output
Differential output pair. LVPECL interface levels.
43, 44
nQA0, QA0 Output
Differential output pair. LVPECL interface levels.
45, 46
nQA1, QA1 Output
Differential output pair. LVPECL interface levels.
47, 48
nQA2, QA2 Output
Differential output pair. LVPECL interface levels.
49, 50
51
52
nQA3, QA3
SYNC_SEL
VCO_SEL
Output
Input
Input
Differential output pair. LVPECL interface levels.
SYNC output select pin. When LOW, the SYNC otuput follows the timing
Pulldown diagram (page 5). When HIGH, QD output follows QC output LVCMOS/
LVTTL interface levels..
Pulldown Selects VCO range. LVCMOS/LVTTL interface levels.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
REVISION B 8/25/15
3
LOW VOLTAGE, LVCMOS/LVPECL-TO LVPECL/ECL
CLOCK GENERATOR