843N001I Datasheet, PDF (15/20 Pages) Integrated Device Technology – Low Voltage, LVCMOS/LVPECL-to-LVPECL/ECL Clock Generator

3. Calculations and Equations.
The purpose of this section is to derive the power dissipated into the load.
LVPECL output driver circuit and termination are shown in Figure 7
873991-147 DATA SHEET
FIGURE 7. LVPECL DRIVER CIRCUIT AND TERMINATION
To calculate worst case power dissipation into the load, use the following equations which assume a 50Ω load, and a termination
voltage of V – 2V.
CCO
•
For
logic
high,
V_OUT
=
V
OH_MAX
=
V
CCO_MAX
–
0.9V
(V_{CCO_MAX} – V ⁾ _{OH_MAX} = 0.9V
• For logic low, V_OUT = V_{OL_MAX} = V – _{CCO_MAX} 1.7V
(V – V ⁾ = 1.7V
CCO_MAX
OL_MAX
Pd_H is power dissipation when the output drives high.
Pd_L is the power dissipation when the output drives low.
Pd_H = [(V – (V – 2V))/R ] * (V – V ) = [(2V – (V – V ^))/R ] * (V – V ) =
OH_MAX
CCO_MAX
L
CCO_MAX
OH_MAX
CCO_MAX
OH_MAX
L
CCO_MAX
OH_MAX
[(2V – 0.9V)/50Ω] * 0.9V = 19.8mW
Pd_L = [(V – (V – 2V))/R ] * (V – V ) = [(2V – (V – V ^))/R ] * (V – V ) =
OL_MAX
CCO_MAX
L
CCO_MAX
OL_MAX
CCO_MAX
OL_MAX
L
CCO_MAX
OL_MAX
[(2V – 1.7V)/50Ω] * 1.7V = 10.2mW
Total Power Dissipation per output pair = Pd_H + Pd_L = 30mW
REVISION B 8/25/15
15
LOW VOLTAGE, LVCMOS/LVPECL-TO LVPECL/ECL
CLOCK GENERATOR