843N001I Datasheet, PDF (17/20 Pages) Integrated Device Technology – Low Voltage, LVCMOS/LVPECL-to-LVPECL/ECL Clock Generator

PACKAGE OUTLINE - Y SUFFIX FOR 52 LEAD LQFP
873991-147 DATA SHEET
REVISION B 8/25/15
TABLE 9. PACKAGE DIMENSIONS
JEDEC VARIATION
ALL DIMENSIONS IN MILLIMETERS
SYMBOL
MINIMUM
BCC
NOMINAL
N
52
A
--
--
A1
0.05
--
A2
1.35
1.40
b
0.22
0.32
c
0.09
--
D
12.00 BASIC
D1
10.00 BASIC
D2
7.80 Ref.
E
12.00 BASIC
E1
10.00 BASIC
E2
7.80 Ref.
e
0.65 BASIC
L
0.45
--
θ
0°
--
ccc
--
--
Reference Document: JEDEC Publication 95, MS-026
MAXIMUM
1.60
0.15
1.45
0.38
0.20
0.75
7°
0.10
17
LOW VOLTAGE, LVCMOS/LVPECL-TO LVPECL/ECL
CLOCK GENERATOR