843N001I Datasheet, PDF (13/20 Pages) Integrated Device Technology – Low Voltage, LVCMOS/LVPECL-to-LVPECL/ECL Clock Generator

873991-147 DATA SHEET
Schematic Layout
Figure 6 shows an example of 873991-147 application
schematic. In this example, the device is operated at V
CC
= V = 3.3V. The decoupling capacitor should be located
CCO
as close as possible to the power pin. The device are be
driven by LVPECL sources.For the LVPECL output drivers,
only two termination examples are shown in this schematic.
Additional termination approaches are shown in the LVPECL
Termination Application Note.
3.3V
Zo = 50 Ohm
Zo = 50 Ohm
LVPECL
Driver_LVPECL
VCC
R3
R4
133
133
R5
82.5
R6
82.5
PCLK
nPCLK
Logic Control Input Examples
Set Logic
VCC
Input to
'1'
RU1
1K
Set Logic
VCC
Input to
'0'
RU2
Not Install
To Logic
Input
pins
RD1
Not Install
To Logic
Input
pins
RD2
1K
VCC
C1
0.1u
VCC
VCC
R9
R10
133
133
VCO_SEL
U1
GND
MR
PLL_EN
REF_SEL
FSEL_FB2
FSEL_FB1
FSEL_FB0
REF_CLK
EXT_FB
nEXT_FB
1
2 ^VEE
3 ^MR
4 ^PLL_EN
5 ^REF_SEL
6 ^FSEL_FB2
7
8
FSEL_FB1
FSEL_FB0
9 ^REF_CLK
10 ^CLK
11 ^nCLK
12 ^VCC
13 ^EXT_FB
nEXT_FB
R14
82.5
R15 VCC
82.5
VCC
R16
10
VCCA
C2
C3
10u
0.01u
VCCO
39
FSEL0 ₃₈
QB2 ₃₇
nQB2 ₃₆
FSEL1 ₃₅
QB1 ₃₄
nQB1
FSEL2
33
32
QB0 ₃₁
nQB0 ₃₀
VCCO ₂₉
QC2 ₂₈
nQC2 ₂₇
FSEL3
FSEL0
FSEL1
FSEL2
FSEL3
QA0
nQA0
VCC=3.3V
VCCO=3.3V
3.3V
R1
133
Zo = 50 Ohm
Zo = 50 Ohm
R7
82.5
R2
133
+
-
R8
82.5
QD1
nQD1
Zo = 50 Ohm
Zo = 50 Ohm
+
-
R11
R12
50
50
Optional
R13
Y-Termination
50
VCCO
(U1,17) VCCO (U1,22)
(U1,30) (U1,42)
C4
0.1u
C5
0.1u
C6
0.1u
C7
0.1u
FIGURE 6. 873991-147 SCHMATIC LAYOUT
REVISION B 8/25/15
13
LOW VOLTAGE, LVCMOS/LVPECL-TO LVPECL/ECL
CLOCK GENERATOR