843N001I Datasheet, PDF (8/20 Pages) Integrated Device Technology – Low Voltage, LVCMOS/LVPECL-to-LVPECL/ECL Clock Generator

873991-147 DATA SHEET
TABLE 6. AC CHARACTERISTICS, V = V = 3.3V ± 5%, TA = 0°C TO 50°C
CC
CCO
Symbol Parameter
Test Conditions Minimum Typical Maximum Units
QA, QB, QC
480
MHz
f
Output Frequency
MAX
QD
QD; NOTE 1
SYNC_SEL = 1
SYNC_SEL = 0
400
MHz
200
MHz
t(Ø)
Static Phase Offset; NOTE
2, 3
CLK, nCLK
170
325
ps
tsk(o) Output Skew; NOTE 4, 5
250
ps
tsk(w) Multiple Frequency Skew; NOTE 5, 6
350
ps
tjit(cc) Cycle-to-Cycle Jitter; NOTE 5
VCO_SEL = 0
VCO_SEL = 1
50
ps
55
ps
tjit(hcyc) Half-Cycle Jitter
NOTE 7
NOTE 8
VCO_SEL = 0
VCO_SEL = 1
375
ps
130
ps
f
PLL VCO Lock Range; NOTE 9
VCO
VCO_SEL = 0
400
VCO_SEL = 1
200
960
MHz
480
MHz
t
LOCK
t /t
R
F
odc
PLL Lock Time
Output Rise/Fall Time
Output Duty Cycle
NOTE 7
NOTE 8
20% to 80%
0.2
VCO_SEL = 0
40
VCO_SEL = 1
45
10
ms
1
ns
60
%
55
%
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is es-
tablished when the device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The
device will meet specifications after thermal equilibrium has been reached under these conditions.
All parameters measured at f unless noted otherwise.
MAX
NOTE 1: SYNC output (QD when SYNC_SEL = 0) operation guaranteed to 800MHz maximum VCO frequency.
NOTE 2: Defined as the time difference between the input reference clock and the average feedback input signal
when the PLL is locked and the input reference frequency is stable.
NOTE 3: Static phase offset is specified for an input frequency of 50MHz with feedback in ÷8.
NOTE 4: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at the output differential cross points.
NOTE 5: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 6: Defined as skew across banks of outputs switching in the same direction operating at different frequencies
with the same supply voltages and equal load conditions. Measured at V /2.
CCO
NOTE 7: This value is based on the VCO frequency = 960MHz, output divider = 2.
NOTE 8: This value is based on the VCO frequency = 480MHz, output divider = 2.
NOTE 9: When VCO_SEL = 0, the PLL will be unstable with feedback configurations of ÷2, ÷4, ÷32 and some ÷6.
When VCO_SEL = 1, the PLL will be unstable with a feedback configuration of ÷2.
REVISION B 8/25/15
8
LOW VOLTAGE, LVCMOS/LVPECL-TO LVPECL/ECL
CLOCK GENERATOR