843N001I Datasheet, PDF (1/20 Pages) Integrated Device Technology – Low Voltage, LVCMOS/LVPECL-to-LVPECL/ECL Clock Generator

Low Voltage, LVCMOS/LVPECL-to-LVPECL/ECL
Clock Generator
843N001I
DATASHEET
GENERAL DESCRIPTION
The 873991-147 is a low voltage, low skew, 3.3V LVPECL or ECL
Clock Generator and a member of the family of High Performance
Clock Solutions from IDT. The 873991-147 has two selectable clock
inputs. The CLK, nCLK pair can accept LVPECL, LVDS, LVHSTL,
SSTL and HCSL input levels and, the REF_CLK pin can accept a
LVCMOS or LVTTL input levels. This device has a fully integrated
PLL along with frequency configurable outputs. An external feedback
input and output regenerates clocks with “zero delay”.
The four independent banks of outputs each have their own output
dividers, which allow the device to generate a multitude of differ-
ent bank frequency ratios and output-to-input frequency ratios.
The output frequency range is 25MHz to 480MHz and the input
frequency range is 6.25MHz to 120MHz. The PLL_EN input can
be used to bypass the PLL for test and system debug purposes.
In bypass mode, the input clock is routed around the PLL and into
the internal output dividers.
The 873991-147 also has a SYNC output which can be used for
system synchronization purposes. It monitors Bank A and Bank
C outputs for coincident rising edges and signals a pulse per the
timing diagrams in this data sheet. This feature is used primarily
in applications where Bank A and Bank C are running at different
frequencies, and is particularly useful when they are running at
non-integer multiples of each other.
Example Applications:
1. Line Card Multiplier: Multiply 19.44MHz from a back-plane
to 77.76MHz on the line card ASIC and Serdes.
2. Zero Delay Buffer: Fan out up to thirteen 100MHz copies
from a reference clock to multiple processing units on an
embedded system.
FEATURES
• Fourteen differential 3.3V LVPECL/ECL outputs
• Selectable differential or REF_CLK inputs
• CLK, nCLK can accept the following input levels:
LVPECL, LVDS, LVHSTL, SSTL, HCSL
• REF_CLK accepts the following input levels: LVCMOS, LVTTL
• Input clock frequency range: 6.25MHz to 120MHz
• Maximum output frequency: 480MHz
• VCO range: 200MHz to 960MHz
• Output skew: 250ps (maximum), outputs at the same frequency
• Cycle-to-cycle jitter: 55ps (maximum)
• LVPECL mode operating voltage supply range:
V = 3.135V to 3.465V, V = 0V
CC
EE
• ECL mode operating voltage supply range:
V = 0V, V = -3.465V to -3.135V
CC
EE
• 0°C to 50°C ambient operating temperature
• Available in lead-free (RoHS 6) package
• Use replacement part 873996AYLF
PIN ASSIGNMENT
873991-147 REVISION B 8/25/15
1
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