843N001I Datasheet, PDF (10/20 Pages) Integrated Device Technology – Low Voltage, LVCMOS/LVPECL-to-LVPECL/ECL Clock Generator

APPLICATIONS INFORMATION
873991-147 DATA SHEET
POWER SUPPLY FILTERING TECHNIQUES
As in any high speed analog circuitry, the power supply pins
are vulnerable to random noise. To achieve optimum jitter per-
formance, power supply isolation is required. The 873991-147
provides separate power supplies to isolate any high switch-
ing noise from the outputs to the internal PLL. V , V , and
CC
CCA
V should be individually connected to the power supply
CCO
plane through vias, and 0.01µF bypass capacitors should be
used for each pin. Figure 2 illustrates this for a generic V pin
CC
and also shows that V requires that an additional10Ω resistor
CCA
along with a 10µF bypass capacitor be connected to the V pin.
CCA
3.3V
V
CC
.01μF 10Ω
V
CCA
.01μF
10μF
FIGURE 2. POWER SUPPLY FILTERING
WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS
Figure 3 shows how the differential input can be wired to accept of R1 and R2 might need to be adjusted to position the V_REF in
single ended levels. The reference voltage V_REF = V /2 is
CC
generated by the bias resistors R1, R2 and C1. This bias circuit
should be located as close as possible to the input pin. The ratio
the center of the input voltage swing. For example, if the input clock
swing is only 2.5V and V = 3.3V, V_REF should be 1.25V and R2/
CC
R1 = 0.609.
V_CC
Single Ended Clock Input
V_REF
C1
0.1u
R1
1K
CLK
nCLK
R2
1K
REVISION B 8/25/15
FIGURE 3. SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT
10
LOW VOLTAGE, LVCMOS/LVPECL-TO LVPECL/ECL
CLOCK GENERATOR