8413S12 Datasheet, PDF (9/33 Pages) Integrated Device Technology – Selectable external crystal or differential

8413S12 DATA SHEET
Table 7C. Jitter Specifications for Network Processor Core Clocks and High Speed PLLs, V_DD = 3.3V ± 5%, V_{DDO_[A:E]} =
3.3V ± 5%; and V_DD = 3.3V ± 5%, V_{DDO_G} = V_{DDO_QREF} = 3.3V ± 5%, T_A = -40°C to 85°C
Symbol
Parameter
Test Conditions
Output Minimum Typical Maximum Units
ƒ= 50MHz, 25MHz Crystal Input,
Internal Processor PLL BW=1MHz
QF
32.8
70
ps
ƒ= 50MHz, 25MHz Crystal Input,
Internal Processor PLL BW=2MHz
QF
J_{CORE_REFCLK}
Total Jitter;
Peak-to-Peak
NOTE 1, 2, 3
ƒ= 50MHz, 25MHz Crystal Input,
Internal Processor PLL BW = 5MHz
QF
ƒ= 50MHz, 25MHz Crystal Input,
Internal Processor PLL BW = 8MHz
QF
33
70.01
ps
33.6
70.05
ps
34.5
71.2
ps
ƒ= 50MHz, 25MHz Crystal Input,
Internal Processor PLL BW = 10MHz
QF
35.3
71.9
ps
ƒ= 125MHz, 25MHz Crystal Input,
High Speed PLL BW = 1MHz
QG
39.5
86.7
ps
ƒ= 125MHz, 25MHz Crystal Input,
High Speed PLL BW = 2MHz
QG
J_{PLL_REFCLK}
Total Jitter,
Peak-to-Peak
NOTE 1, 2, 3
ƒ= 125MHz, 25MHz Crystal Input,
High Speed PLL BW = 5MHz
QG
ƒ= 125MHz, 25MHz Crystal Input,
High Speed PLL BW = 8MHz
QG
39.5
86.7
ps
39.9
86.9
ps
41.6
88.4
ps
ƒ= 125MHz, 25MHz Crystal Input,
High Speed PLL BW = 10MHz
QG
43.3
90
ps
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is
mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium
has been reached under these conditions. For additional information, refer to the Network Processor Core Clocks and High Speed PLLs
Application Note section in the datasheet.
NOTE 1: Total phase jitter after applying the evaluation bands to the system transfer function for Network Processor Clock Architecture and
High Speed PLLs. The transfer function is defined and illustrated in the Network Processor Core Clocks and High Speed PLLs Application
Note section in the datasheet.
NOTE 2: Measurement in the Frequency Domain. Evaluation Band with PLL mask applied: 10Hz - 40MHz.
NOTE 3: Jitter data is measured with Agilent E5052A Signal Source Analyzer.
Table 7D. AC Characteristics, V_DD = 3.3V ± 5%, V_{DDO_[A:E]} = V_{DDO_F} = 3.3V ± 5%; and
V_DD = 3.3V ± 5%, V_{DDO_G} = V_{DDO_QREF} = 3.3V ± 5% or 2.5V ± 5%, T_A = -40°C to 85°C
Symbol Parameter
Test Conditions
Output
Minimum
FSEL_[A:E] = 00
Q[A:E], nQ[A:E]
FSEL_[A:E] = 01
Q[A:E], nQ[A:E]
FSEL_[A:E] = 10
Q[A:E], nQ[A:E]
f_OUT
Output Frequency
FSEL_[A:E] = 11
Q[A:E], nQ[A:E]
QF
QG
QREF[0:1]
Typical
100
125
156.25
312.5
50
125
25
Maximum
Units
MHz
MHz
MHz
MHz
MHz
MHz
MHz
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is
mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium
has been reached under these conditions.
REVISION D 1/27/15
9
HCSL/ LVCMOS CLOCK GENERATOR