8413S12 Datasheet, PDF (8/33 Pages) Integrated Device Technology – Selectable external crystal or differential

8413S12 DATA SHEET
Table 6. Input Frequency Characteristics, V_DD = 3.3V ± 5%, V_{DDO_[A:E]} = V_{DDO_F} = 3.3V ± 5%; or
V_DD = 3.3V ± 5%, V_{DDO_G} = V_{DDO_QREF} = 3.3V ± 5% or 2.5V ± 5%, T_A = -40°C to 85°C
Symbol Parameter
Test Conditions
Minimum Typical
F_IN
Input
Frequency
CLK, nCLK
XTAL_IN, XTAL_OUT
25
25
Maximum
Units
MHz
MHz
AC Electrical Characteristics
Table 7A. PCI Express Jitter Specifications, V_DD = 3.3V ± 5%, V_{DDO_[A:E]} = 3.3V ± 5%; and V_DD = 3.3V ± 5%, V_{DDO_G} =
V_{DDO_QREF} = 3.3V ± 5%, T_A = -40°C to 85°C
Symbol
Parameter
Test Conditions
PCIe Industry
Minimum Typical Maximum Specification Units
t_j
Phase Jitter
Peak-to-Peak;
(PCIe Gen 1) _{NOTE 1, 4}
ƒ= 100MHz, 25MHz Crystal Input
Evaluation Band: 0Hz - Nyquist
(clock frequency/2)
14.27
24.35
86
ps
t_{REFCLK_HF_R}
MS
(PCIe Gen 2)
Phase Jitter RMS;
NOTE 2, 4
ƒ= 100MHz, 25MHz Crystal Input
High Band: 1.5MHz - Nyquist
(clock frequency/2)
1.47
3.04
3.10
ps
t_{REFCLK_LF_R}
MS
(PCIe Gen 2)
Phase Jitter RMS;
NOTE 2, 4
ƒ= 100MHz, 25MHz Crystal Input
Low Band: 10kHz - 1.5MHz
0.17
0.67
3.0
ps
t_{REFCLK_RMS Phase Jitter RMS;}
(PCIe Gen 3) ^{NOTE 3, 4}
ƒ= 100MHz, 25MHz Crystal Input
Evaluation Band: 0Hz - Nyquist
(clock frequency/2)
0.37
0.79
0.8
ps
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is
mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium
has been reached under these conditions. For additional information, refer to the PCI Express Application Note section in the datasheet.
NOTE 1: Peak-to-Peak jitter after applying system transfer function for the Common Clock Architecture. Maximum limit for PCI Express Gen 1
is 86ps peak-to-peak for a sample size of 10⁶ clock periods.
NOTE 2: RMS jitter after applying the two evaluation bands to the two transfer functions defined in the Common Clock Architecture and
reporting the worst case results for each evaluation band. Maximum limit for PCI Express Generation 2 is 3.1ps RMS for t_{REFCLK_HF_RMS}
(High Band) and 3.0ps RMS for t_{REFCLK_LF_RMS} (Low Band).
NOTE 3: RMS jitter after applying system transfer function for the common clock architecture. This specification is based on the PCI Express
Base Specification Revision 0.7, October 2009 and is subject to change pending the final release version of the specification.
NOTE 4: This parameter is guaranteed by characterization. Not tested in production.
Table 7B. Serial Rapid IO Switch Jitter Specification, V_DD = 3.3V ± 5%, V_{DDO_[A:E]} = 3.3V ± 5%; and V_DD = 3.3V ± 5%,
V_{DDO_G} = V_{DDO_QREF} = 3.3V ± 5%, T_A = -40°C to 85°C
Symbol Parameter
Test Conditions
IDT sRIO
Minimum Typical Maximum Specification Units
J_{CLK_REF}
Total Phase Jitter, RMS; ƒ= 125MHz, 25MHz Crystal Input,
NOTE 1, 2, 3, 4
HCSL Output Clocks
0.64
1.55
3
ps
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is
mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium
has been reached under these conditions. For additional information, refer to the Serial Rapid IO Application Note section in the datasheet.
NOTE 1: Total phase jitter after applying the evaluation bands to the system transfer function for the IDT sRIO Tsi57x and Tsi620 Product
Families. The transfer function is defined and illustrated in the Serial Rapid IO Application Note section in the datasheet and the IDT hardware
manual of the Tsi57x and Tsi620. Total RMS phase jitter allowed on the reference clock of the Tsi57x and Tsi620 is specified at 3ps (max).
NOTE 2: Evaluation band with sRIO mask applied: 10Hz - 40MHz.
NOTE 3: Total phase jitter includes random and deterministic jitter.
NOTE 4: Jitter data is measured with Agilent E5052A Signal Source Analyzer.
HCSL/ LVCMOS CLOCK GENERATOR
8
REVISION D 1/27/15