8413S12 Datasheet, PDF (26/33 Pages) Integrated Device Technology – Selectable external crystal or differential

8413S12 DATA SHEET
Serial Rapid IO Application Note
The Serial Rapid IO jitter analysis methodology models the system
response to reference clock jitter. The total RMS phase jitter allowed
on the reference clock of the Tsi57x and Tsi620 is specified at 3ps
(max). In this jitter analysis, the TSI57x and Tsi620 SERDES PLL is
modeled by the transfer response function H(s) shown in Figure 7. To
model the response of the switch on the reference clock jitter, a
phase noise measurement is executed and a frequency domain
analysis is performed. In the phase noise plot, the mask of the
transfer function H(s) is applied to the phase noise response of the
reference clock. The area under the resultant phase noise curve is
referred to as Phase Jitter. In the frequency domain, the random and
deterministic jitter can be calculated quickly and accurately. RMS
Phase Jitter is also referred to as random jitter and the spurs on the
phase noise plot can be interpreted as deterministic jitter. Total RMS
Phase Jitter includes both random and deterministic jitter.
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Figure 7. Weighing Function for Jitter Calculation
Network Processor Core Clocks and High Speed PLLs Application Note
The Network Processor Core clocks and High Speed PLLs jitter
analysis models the system response to reference clock jitter.
Network Processors typically have internal high speed PLLs that
scale external reference core clocks 10x, 20x and 40x the input
frequency. In this jitter analysis, the high speed PLLs internal to the
processors are modeled by the transfer response function shown in
Figure 8. A phase noise measurement is executed and a frequency
domain analysis is performed. In the phase noise plot, the high speed
PLL transfer function is masked on the reference clock. The area
under the resultant phase noise curve is referred to as Phase Jitter.
In the frequency domain, the random and deterministic jitter can be
calculated quickly and accurately. RMS Phase Jitter is also referred
to as random jitter and the spurs on the phase noise plot can be
interpreted as deterministic jitter. Total Phase Jitter includes both
Random and Deterministic jitter. The Total Jitter can then be
calulated using a desired bit error rate (BER). For additional
information on calculating Total Jitter refer to the Peak-to-Peak Jitter
Calculations section.
Magnitude
0 dB
-20dB/Decade
BW
Frequency
Figure 8. Weighing Function for Jitter Calculation
HCSL/ LVCMOS CLOCK GENERATOR
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REVISION D 1/27/15