8413S12 Datasheet, PDF (23/33 Pages) Integrated Device Technology – Selectable external crystal or differential

8413S12 DATA SHEET
Schematic Example
Figure 6 (next page) shows an example of 8413S12 application
schematic. The schematic example focuses on functional
connections and is not configuration specific. Refer to the pin
description and functional tables in the datasheet to ensure that the
logic control inputs are properly set. In this example, the device is
operated at V_DD = V_{DDO_A} = V_{DDO_B} = V_{DDO_C} = V_{DDO_D} = V_{DDO_E}
= V_{DDO_F} = 3.3v and V_{DDO_QREF} = 3.3V.
The 18pF parallel resonant 25MHz crystal is used. The load
capacitance C1 = 22pF and C2 = 10pF are recommended for
frequency accuracy. Depending on the parasitic of the printed circuit
board layout, these values might require a slight adjustment to
optimize the frequency accuracy. Crystals with other load
capacitance specifications can be used. This will require adjusting
C1 and C2. For this device, the crystal load capacitors are required
for proper operation.
Crystal layout is very important to minimize capacitive coupling
between the crystal pads and leads and other metal in the circuit
board. Capacitive coupling to other conductors has two adverse
effects; it reduces the oscillator frequency leaving less tuning margin
and noise coupling from power planes and logic transitions on signal
traces can pull the phase of the crystal resonance, inducing jitter.
Routing I²C under the crystal is a very common layout error, based
on the assumption that it is a low frequency signal and will not affect
the crystal oscillation. In fact, I²C transition times are short enough to
capacitively couple into the crystal if they are routed close enough to
the crystal traces.
In layout, all capacitive coupling to the crystal from any signal trace is
to be minimized, that is to the XTAL_IN and XTAL_OUT pins, traces
to the crystal pads, the crystal pads and the tuning capacitors. Using
a crystal on the top layer as an example, void all signal and power
layers under the crystal connections between the top layer and the
ground plane used by the 8413S12. Then calculate the parasitic
capacity to the ground and determine if it is large enough to preclude
tuning the oscillator. If the coupling is excessive, particularly if the first
layer under the crystal is a ground plane, a layout option is to void the
ground plane and all deeper layers until the next ground plane is
reached. The ground connection of the tuning capacitors should first
be made between the capacitors on the top layer, then a single
ground via is dropped to connect the tuning cap ground to the ground
plane as close to the 8413S12 as possible as shown in the
schematic.
As with any high speed analog circuitry, the power supply pins are
vulnerable to random noise. To achieve optimum jitter performance,
power supply isolation is required. The 8413S12 provides separate
power supplies to isolate any high switching noise from coupling into
the internal PLL.
In order to achieve the best possible filtering, it is recommended that
the placement of the filter components be on the device side of the
PCB as close to the power pins as possible. The 0.1uf capacitor in
each power pin filter and the 10 ohm VDDA filter resistor must be
placed on the device side of the board. If space is limited, the other
bulk filtering components can be on the side opposite the device side
of the PCB.
Power supply filter recommendations are a general guideline to be
used for reducing external noise from coupling into the devices. The
filter performance is designed for a wide range of noise frequencies.
This low-pass filter starts to attenuate noise at approximately 10 kHz.
If a specific frequency noise component is known, such as switching
power supplies frequencies, it is recommended that component
values be adjusted and if required, additional filtering be added.
REVISION D 1/27/15
23
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