8413S12 Datasheet, PDF (24/33 Pages) Integrated Device Technology – Selectable external crystal or differential

8413S12 DATA SHEET
Logic Control Input Examples
Set Logic
Set Logic
VDD _{Input to '1'} VD D _{Input to '0'}
R U1
1K
R U2
N ot In sta ll
VDDO
C1 0
0. 1u
To Lo gic
Inp ut
pin s
To Log ic
Inpu t
pin s
VDD O_Q REF
R D1
N ot I nst all
R D2
1K
C4
0. 1u
U1
R 6 10
VDD
C6
1 0u
C1
22 pF
X1
25 M₁ H_{8 p} z_F
VDD A
C7
0. 1u
FSEL_ A0
FSEL_ A1
FSEL_ B0
FSEL_ B1
FSEL_ C0
FSEL_ C1
FSEL_ D0
FSEL_ D1
FSEL_ E0
FSEL_ E1
XTAL_ IN
R EF_ SEL
XTAL _OU T
C2
10 pF
1
2 ^GND
3 ^{FSEL _A0}
4 ^{FSEL _A1}
5 ^{FSEL _B0}
6 FSEL _B1
7 ^{FSEL _C0}
8 ^{FSEL _C1}
9 ^{FSEL _D0}
10 ^{FSEL _D1}
11 ^{FSEL _E0}
12 ^VDDA
13 ^{FSEL _E1}
14 ^nc
15 ^{XTAL _I N}
16 ^{XTAL _OU T}
17 ^nc
18 ^REF_SEL
GND
VDDO
C 11
0 .1 u
R 1 33
Q A0
VD DO
R 3 33
nQ A0
C3
0. 1u
Zo = 50
+
Zo = 50
-
R4 R5 _{Us e for PCI Express}
50
50
Add-In Card
VDD
C5
0 .1u
R2
4 75
54
nc _{5 3}
VDD _{5 2}
IR EF _{5 1}
O E_D 5 0
nQ D1 _{4 9}
Q D1 _{4 8}
nQ D0 _{4 7}
Q D0 _{4 6}
VDDO _D _{4 5}
VDDO _C _{4 4}
nQ C1 _{4 3}
Q C1 _{4 2}
nQ C0 _{4 1}
Q C0 _{4 0}
O E_C _{3 9}
VDD _{3 8}
G ND _{3 7}
nc
O E_D
nQD 1
QD1
nQC 0
QC0
nQC 1
QC1
nQC 0
QC0
O E_ C
VDDO
C8
0 .1 u
VD DO
C9
0 .1u
VDD
C12
0. 1u
HCSL Termination
Zo = 5 0
Zo = 5 0
LVPECL Dr vi e r
VDD
R9
12 5
VD D
R1 0
12 5
C1 3
0. 1u
R1 3
84
R1 4
84
CLK
nCL K
VD DO
VD DO
C1 4
0. 1u
C1 5
0. 1u
Opti ona l
R7 3 3
Q E1 _{Zo = 5 0}
R8 3 3
n QE1 Zo = 5 0
+
R1 1
50
-
R1 2
50
Us e for PCI Express
Point-to-Point Connec tion
3 .3 V
BL M18 BB2 21 SN 1
1
2
C 16
0. 1u F
Fer rit e Be ad C1 7
1 0uF
VDD
3. 3V
BLM18BB2 21SN 1
1
2
VD DO_ QR EF
C1 8
0.1 uF
Fer rite Bea d C19
10 uF
3 .3 V
BL M18 BB2 21 SN 1
1
2
VDDO
C 20
0. 1u F
Fer rit e Be ad C2 1
1 0uF
VD D=V DD O_A =V DD O_ B =3. 3 V
VD DO_C= VD DO_D=V DD O_E=3 .3V
VD DO_F=VD DO_ QREF=3.3V
QREF1
R 15 35
Zo = 50
L VC MOS
Figure 6. 8413S12 Schematic Example
HCSL/ LVCMOS CLOCK GENERATOR
24
REVISION D 1/27/15