8413S12 Datasheet, PDF (2/33 Pages) Integrated Device Technology – Selectable external crystal or differential

8413S12 DATA SHEET
Block Diagram
nMR
Pullup
FSEL_A [0:1] ^Pulldown
2
FSEL_B [0:1] ^Pulldown
2
FSEL_C [0:1] ^Pulldown
2
FSEL_D [0:1] ^Pulldown
2
FSEL_E [0:1] ^Pulldown
2
PLL_SEL ^Pullup
REF_SEL ^Pullup
Pulldown
CLK,
nCLK
Pullup/
0
Pulldown
1
XTAL_IN
OSC
XTAL_OUT
IREF
Clock
Output
Control
Logic
VCO
NOTE: OE_[A:G] and OE_REF pins have pullup resistors.
00 = 100MHz
01 = 125MHz
10 = 156.25MHz
11 = 312.5MHz
00 = 100MHz
01 = 125MHz
10 = 156.25MHz
11 = 312.5MHz
00 = 100MHz
01 = 125MHz
10 = 156.25MHz
11 = 312.5MHz
00 = 100MHz
01 = 125MHz
0
10 = 156.25MHz
11 = 312.5MHz
1
00 = 100MHz
01 = 125MHz
10 = 156.25MHz
11 = 312.5MHz
50MHz
125MHz
OE_REF
OE_A
QA0,
nQA0
QA1,
nQA1
OE_B
QB0,
nQB0
QB1,
nQB1
OE_C
QC0,
nQC0
QC1,
nQC1
OE_D
QD0,
nQD0
QD1,
nQD1
OE_E
QE0,
nQE0
QE1,
nQE1
QF
OE_G
QG
QREF0
QREF1
HCSL/ LVCMOS CLOCK GENERATOR
2
REVISION D 1/27/15