8413S12 Datasheet, PDF (11/33 Pages) Integrated Device Technology – Selectable external crystal or differential

8413S12 DATA SHEET
Table 7G. HCSL AC Characteristics, V_DD = 3.3V ± 5%, V_{DDO_[A:E]} = V_{DDO_F} = 3.3V ± 5%; and
V_DD = 3.3V ± 5%, V_{DDO_G} = V_{DDO_QREF} = 3.3V ± 5% or 2.5V ± 5%, T_A = -40°C to 85°C
Symbol Parameter
Output Configurations
Outputs
Minimum Typical
QA, nQA
3
QA = QD = 100MHz,
QB = QG = 125MHz,
QB, nQB
3
R_J
Random Jitter
QC = QE = 156.25MHz,
QC, nQC
3
QF = 50MHz,
QD, nQD
3
QREF0 = QREF1 = 25MHz
QE, nQE
3
QA, nQA
20
QA = QD = 100MHz,
QB = QG = 125MHz,
QB, nQB
43
D_J
Deterministic Jitter
QC = QE = 156.25MHz,
QC, nQC
64
QF = 50MHz,
QD, nQD
30
QREF0 = QREF1 = 25MHz
QE, nQE
70
RMS Phase Jitter, (Random)
Integration Range:
(10kHz to 1.5MHz)
QA, nQA;
QD, nQD
0.66
RMS Phase Jitter, (Random)
Integration Range:
QA = QD = 100MHz,
(1.5MHz to 50MHz)
QB = QG = 125MHz,
QA, nQA;
QD, nQD
0.56
tjit(Ø)
QC = QE = 156.25MHz,
RMS Phase Jitter, (Random) _{QF = 50MHz,}
Integration Range:
QREF0 = QREF1 = 25MHz
(20MHz to 78.125MHz)
QC, nQC;
QE, nQE
0.34
RMS Phase Jitter, (Random)
Integration Range:
(12kHz to 50MHz)
QC, nQC;
QE, nQE
0.85
Maximum
5
5
5
5
5
50
100
100
80
120
Units
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
0.76
ps
0.68
ps
0.48
ps
0.95
ps
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is
mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium
has been reached under these conditions.
NOTE: Refer to Applications Section for peak-to-peak jitter calculations.
REVISION D 1/27/15
11
HCSL/ LVCMOS CLOCK GENERATOR