8413S12 Datasheet, PDF (5/33 Pages) Integrated Device Technology – Selectable external crystal or differential

Function Tables
Table 3A. FSEL_X Control Input Function Table
Input
Output Frequency
FSEL_X[0:1]
Q[Ax:Ex], nQ[Ax:Ex]
00 (default)
100MHz
01
125MHz
10
156.25MHz
11
312.50MHz
NOTE: FSEL_X denotes FSEL_A, _B, _C, _D, _E.
NOTE Any two outputs operated at the same frequency will be
synchronous.
Table 3B. PLL_SEL Control Input Function Table
Input
PLL_SEL
Operation
0
PLL Bypass
1 (default)
PLL Mode
Table 3C. REF_SEL Control Input Function Table
Input
REF_SEL
Clock Source
0
CLK, nCLK
1 (default)
XTAL_IN, XTAL_OUT
8413S12 DATA SHEET
Table 3D. OE_[A:E] Control Input Function Table
Input
Outputs
OE_[A:E]
Q[Ax:Ex], nQ[Ax:Ex]
0
High-Impedance
1 (default)
Enabled
Table 3E. OE_G Control Input Function Table
Input
Outputs
OE_G
QG
0
High-Impedance
1 (default)
Enabled
Table 3F. OE_REF Control Input Function Table
Input
Output
OE_REF
QREF[0:1]
0
High-Impedance
1 (default)
Enabled
REVISION D 1/27/15
5
HCSL/ LVCMOS CLOCK GENERATOR