8413S12 Datasheet, PDF (19/33 Pages) Integrated Device Technology – Selectable external crystal or differential

8413S12 DATA SHEET
Differential Clock Input Interface
The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, HCSL and other
differential signals. Both signals must meet the V_PP and V_CMR input
requirements. Figures 2A to 2E show interface examples for the
CLK/nCLK input driven by the most common driver types. The input
interfaces suggested here are examples only. Please consult with the
vendor of the driver component to confirm the driver termination
requirements. For example, in Figure 2A, the input termination
applies for IDT open emitter LVHSTL drivers. If you are using an
LVHSTL driver from another vendor, use their termination
recommendation.
1.8V
Zo = 50Ω
Zo = 50Ω
LVHSTL
IDT
LVHSTL Driver
3.3V
CLK
R1
R2
50Ω
50Ω
nCLK
Differential
Input
Figure 2A. CLK/nCLK Input Driven by an
IDT Open Emitter LVHSTL Driver
Figure 2B. CLK/nCLK Input Driven by a
3.3V LVPECL Driver
3.3V
*R3
*R4
HCSL
3.3V
CLK
nCLK
Differential
Input
Figure 2C. CLK/nCLK Input Driven by a
3.3V LVPECL Driver
Figure 2D. CLK/nCLK Input Driven by a
3.3V HCSL Driver
Figure 2E. CLK/nCLK Input Driven by a 3.3V LVDS Driver
REVISION D 1/27/15
19
HCSL/ LVCMOS CLOCK GENERATOR