7133LA70GB Datasheet, PDF (8/16 Pages) Integrated Device Technology – HIGH SPEED 2K X 16 DUAL-PORT SRAM

IDT7133SA/LA, IDT7143SA/LA
High-Speed 2K x 16 Dual-Port RAM
Military, Industrial and Commercial Temperature Ranges
TIMING WAVEFORM OF READ CYCLE NO. 1, EITHER SIDE⁽⁵⁾
tRC
ADDRESS
tAA
DATAOUT
tOH
PREVIOUS DATA VALID
tOH
DATA VALID
BUSYOUT
tBDD^(3,4)
2746 drw 07
TIMING WAVEFORM OF READ CYCLE NO. 2, EITHER SIDE⁽⁵⁾
tACE ⁽⁴⁾
CE
tAOE ⁽⁴⁾
tHZ ⁽²⁾
OE
tLZ ⁽¹⁾
tHZ ⁽²⁾
DATAOUT
ICC
CURRENT
ISB
tLZ ⁽¹⁾
tPU
50%
VALID DATA
tPD
50%
2746 drw 08
NOTES:
1. Timing depends on which signal is asserted last, OE or CE.
2. Timing depends on which signal is deasserted first, OE or CE.
3. tBDD delay is required only in a case where the opposite port is completing a write operation to the same address location. For simultaneous read operations, BUSY has no
relationship to valid output data.
4. Start of valid data depends on which timing becomes effective last, tAOE, tACE, tAA, or tBDD.
5. R/W = VIH, and the address is valid prior to or coincidental with CE transition LOW.
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