7133LA70GB Datasheet, PDF (12/16 Pages) Integrated Device Technology – HIGH SPEED 2K X 16 DUAL-PORT SRAM

IDT7133SA/LA, IDT7143SA/LA
High-Speed 2K x 16 Dual-Port RAM
Military, Industrial and Commercial Temperature Ranges
Timing Waveform of Write with Port-to-Port Read and BUSY^(1,2,3)
tWC
ADDR"A"
MATCH
tWP
R/W"A"
tDW
tDH
DATAIN"A"
tAPS⁽¹⁾
VALID
ADDR"B"
BUSY"B"
MATCH
tBDA
tBDD
tWDD
DATAOUT "B"
tDDD⁽⁴⁾
NOTES:
1. To ensure that the earlier of the two ports wins, tAPS is ignored for Slave (IDT7143).
2. CEL = CER = VIL
3. OE = VIL for the reading port.
4. All timing is the same for left and right ports. Port "A" may be either the left or right port. Port "B" is the port opposite from port "A".
VALID
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Timing Waveform of Write with BUSY⁽³⁾
tWP
R/W"A"
tWB
BUSY"B"
tWH(1)
R/W"B"
(2)
,
NOTES:
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1. tWH must be met for both BUSY input (IDT7143, slave) and output (IDT7133, master).
2. BUSY is asserted on port "B" blocking R/W"B", until BUSY"B" goes HIGH.
3. All timing is the same for left and right ports. Port "A" may be either left or right port. Port "B" is the opposite from port "A".
61.422