7133LA70GB Datasheet, PDF (15/16 Pages) Integrated Device Technology – HIGH SPEED 2K X 16 DUAL-PORT SRAM

IDT7133SA/LA, IDT7143SA/LA
High-Speed 2K x 16 Dual-Port RAM
Military, Industrial and Commercial Temperature Ranges
Truth Table I – Non-Contention Read/Write Control⁽⁴⁾
LEFT OR RIGHT PORT⁽¹⁾
R/WLB R/WUB
CE
OE
I/O0-7
I/O8-15
Function
X
X
H
X
Z
Z
Port Disabled and in Power Down Mode, ISB2, ISB4
X
X
H
X
Z
Z
CER = CEL = VIH, Power Down Mode, ISB1 or ISB3
L
L
L
X
DATAIN
DATAIN Data on Lower Byte and Upper Byte Written into Memory⁽²⁾
L
H
L
L
DATAIN
DATAOUT Data on Lower Byte Written into Memory⁽²⁾, Data in Memory Output on
Upper Byte⁽³⁾
H
L
L
L
DATAOUT
DATAIN Data in Memory Output on Lower Byte⁽³⁾, Data on Upper Byte Written into
Memory⁽²⁾
L
H
L
H
DATAIN
Z
Data on Lower Byte Written into Memory⁽²⁾
H
L
L
H
Z
DATAIN Data on Upper Byte Written into Memory ⁽²⁾
H
H
L
L
DATAOUT
DATAOUT Data in Memory Output on Lower Byte and Upper Byte
H
H
L
H
Z
Z
High Impedance Outputs
NOTES:
1. A0L - A10L≠A0R - A10R
2. If BUSY = LOW, data is not written.
3. If BUSY = LOW, data may not be valid, see tWDD and tDDD timing.
4. "H" = HIGH, "L" = LOW, "X" = Don’t Care, "Z" = High-Impedance, "LB" = Lower Byte, "UB" = Upper Byte
2746 tbl 13
Truth Table II — Address BUSY
Arbitration
Inputs
Outputs
CEL CER
A0L-A10L
A0R-A10R
BUSYL⁽¹⁾ BUSYR⁽¹⁾
Function
X X NO MATCH
H
H
Normal
HX
MATCH
H
H
Normal
XH
MATCH
H
H
Normal
LL
MATCH
(2)
(2)
Write Inhibit⁽³⁾
NOTES:
2746 tbl 14
1. Pins BUSYL and BUSYR are both outputs on the IDT7133 (MASTER). Both are
inputs on the IDT7143 (SLAVE). On Slaves the BUSY input internally inhibits
writes.
2. "L" if the inputs to the opposite port were stable prior to the address and enable
inputs of this port. “H” if the inputs to the opposite port became stable after the
address and enable inputs of this port. If tAPS is not met, either BUSYL or BUSYR
= VIL will result BUSYL and BUSYR outputs can not be LOW simultaneously.
3. Writes to the left port are internally ignored when BUSYL outputs are driving LOW
regardless of actual logic level on the pin. Writes to the right port are internally
ignored when BUSYR outputs are driving LOW regardless of actual logic level on
the pin.
61.452