7133LA70GB Datasheet, PDF (13/16 Pages) Integrated Device Technology – HIGH SPEED 2K X 16 DUAL-PORT SRAM

IDT7133SA/LA, IDT7143SA/LA
High-Speed 2K x 16 Dual-Port RAM
Military, Industrial and Commercial Temperature Ranges
Timing Waveform of BUSY Arbitration Controlled by CE Timing⁽¹⁾
ADDR"A" AND "B"
ADDRESSES MATCH
CE"A"
CE"B"
BUSY"B"
tAPS⁽²⁾
tBAC
tBDC
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Timing Waveform of BUSY Arbitration Controlled by Addresses⁽¹⁾
ADDR "A"
ADDR "B"
BUSY "B"
tRC OR tWC
ADDRESSES MATCH
tAPS⁽²⁾
tBAA
ADDRESSES DO NOT MATCH
tBDA
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NOTES:
1. All timing is the same for left and right ports. Port "A" may be either the left or right port. Port "B" is the port opposite from port "A".
2. If tAPS is not satisfied, the BUSY will be asserted on one side or the other, but there is no guarantee on which side BUSY will be asserted
(IDT7133 only).
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