|
7133LA70GB Datasheet, PDF (1/16 Pages) Integrated Device Technology – HIGH SPEED 2K X 16 DUAL-PORT SRAM | |||
|
HIGH SPEED
2K X 16 DUAL-PORT
SRAM
IDT7133SA/LA
IDT7143SA/LA
Features
â High-speed access
â Military: 25/35/45/55/70/90ns (max.)
â Industrial: 25/35/55ns (max.)
â Commercial: 20/25/35/45/55/70/90ns (max.)
â Low-power operation
â IDT7133/43SA
Active: 1150mW (typ.)
Standby: 5mW (typ.)
â IDT7133/43LA
Active: 1050mW (typ.)
Standby: 1mW (typ.)
â Versatile control for write: separate write control for lower
and upper byte of each port
â MASTER IDT7133 easily expands data bus width to 32 bits
or more using SLAVE IDT7143
â On-chip port arbitration logic (IDT7133 only)
â BUSY output flag on IDT7133; BUSY input on IDT7143
â Fully asynchronous operation from either port
â Battery backup operationâ2V data retention
â TTL-compatible; single 5V (±10%) power supply
â Available in 68-pin ceramic PGA, Flatpack, PLCC and 100-
pin TQFP
â Military product compliant to MIL-PRF-38535 QML
â Industrial temperature range (â40°C to +85°C) is available
for selected speeds
â Green parts available, see ordering information
Description
The IDT7133/7143 are high-speed 2K x 16 Dual-Port Static RAMs.
The IDT7133 is designed to be used as a stand-alone 16-bit Dual-Port
Functional Block Diagram
R/WLUB
CEL
R/WRUB
CER
R/WLLB
OEL
R/WRLB
OER
I/O8L - I/O15L
I/O0L - I/O7L
BUSYL(1)
A10L
A0L
I/O
CONTROL
I/O
CONTROL
ADDRESS
DECODER
11
CEL
MEMORY
ARRAY
ARBITRATION
LOGIC
(IDT7133 ONLY)
ADDRESS
DECODER
11
CER
I/O8R - I/O15R
I/O0R - I/O7R
BUSY R(1)
A10R
A0R
NOTE:
1. IDT7133 (MASTER): BUSY is open drain output and requires pull-up resistor.
IDT7143 (SLAVE): BUSY is input.
1
©2008 Integrated Device Technology, Inc.
2746 drw 01
OCTOBER 2008
DSC 2746/13
|
▷ |