7133LA70GB Datasheet, PDF (3/16 Pages) Integrated Device Technology – HIGH SPEED 2K X 16 DUAL-PORT SRAM

IDT7133SA/LA, IDT7143SA/LA
High-Speed 2K x 16 Dual-Port RAM
Pin Configurations^(1,2,3) (con't.)
Military, Industrial and Commercial Temperature Ranges
51
50
48
46
44
42
40
38
36
11
A6L
A5L
A3L
A1L BUSYL CER
A0R
A2R
A4R
53
52
49
47
45
43
41
39
37
35
34
10
A8L
A7L
A4L
A2L
A0L
CEL BUSYR A1R
A3R
A5R
A6R
55
54
09
A10L
A9L
32
A8R
33
A7R
57
56
08
R/WLLB OEL
30
A10R
31
A9R
59
58
07
VCC(1) R/WLUB
61
60
06
I/O1L I/O0L
63
62
05
I/O3L I/O2L
IDT7133/43G
GU68-1⁽⁴⁾
68-Pin PGA
Top View⁽⁵⁾
28
29
R/WRLB OER
26
27
GND⁽²⁾ R/WRUB
24
25
I/O14R I/O15R
65
64
04
I/O5L I/O4L
22
23
I/O12R I/O13R
67
66
03
I/O7L I/O6L
20
21
I/O10R I/O11R
68
1
3
5
7
9
11
13
15
18
19
02
I/O8L I/O9L I/O11L I/O13L I/O15L GND⁽²⁾ I/O1R I/O3R I/O5R I/O8R I/O9R
2
4
6
8
10
12
14
16
17
01
I/O10L I/O12L I/O14L VCC(1) I/O0R I/O2R I/O4R I/O6R I/O7R
Pin 1
Designator ^A
B
C
D
E
F
G
H
J
K
L
NOTES:
1. Both VCC pins must be connected to the power supply to ensure reliable operation.
2. Both GND pins must be connected to the ground supply to ensure reliable operation.
3. Package body is approximately 1.18 in x 1.18 in x 0.16 in.
4. This package code is used to reference the package diagram.
5. This text does not indicate orientation of the actual part-marking.
2746 drw 04
Pin Names
Left Port
Right Port
CEL
R/WLUB
CER
R/WRUB
R/WLLB
R/WRLB
OEL
OER
A0L - A10L
A0R - A10R
I/O0L - I/O15L I/O0R - I/O15R
BUSYL
BUSYR
VCC
GND
Names
Chip Enable
Upper Byte Read/Write Enable
Lower Byte Read/Write Enable
Output Enable
Address
Data Input/Output
Busy Flag
Power
Ground
2746 tbl 01
6.342